--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: K.31
--  \   \         Application: netgen
--  /   /         Filename: rgb2hy_timesim.vhd
-- /___/   /\     Timestamp: Tue Jan 20 22:44:31 2009
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -s 4 -pcf rgb2hy.pcf -rpw 100 -tpw 0 -ar Structure -tm rgb2hy -insert_pp_buffers false -w -dir netgen/par -ofmt vhdl -sim rgb2hy.ncd rgb2hy_timesim.vhd 
-- Device	: 3s200tq144-4 (PRODUCTION 1.39 2008-01-09)
-- Input file	: rgb2hy.ncd
-- Output file	: /home/remy/robotter/robotter/trunk/eurobot/fpgas/camera/ISE/netgen/par/rgb2hy_timesim.vhd
-- # of Entities	: 1
-- Design Name	: rgb2hy
-- Xilinx	: /opt/Xilinx/10.1/ISE
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity rgb2hy is
  port (
    clk_i : in STD_LOGIC := 'X'; 
    H_o : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    Y_o : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    G_i : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    B_i : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    R_i : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end rgb2hy;

architecture Structure of rgb2hy is
  signal min_s_cmp_le0000 : STD_LOGIC; 
  signal N55 : STD_LOGIC; 
  signal min_s_cmp_le0001 : STD_LOGIC; 
  signal R_i_7_IBUF_1271 : STD_LOGIC; 
  signal min_s_cmp_le0002 : STD_LOGIC; 
  signal B_i_7_IBUF_1273 : STD_LOGIC; 
  signal min_s_cmp_le0003 : STD_LOGIC; 
  signal G_i_7_IBUF_1275 : STD_LOGIC; 
  signal min_s_7_0 : STD_LOGIC; 
  signal offset_s_cmp_ge0000 : STD_LOGIC; 
  signal N79 : STD_LOGIC; 
  signal offset_s_cmp_ge0001 : STD_LOGIC; 
  signal R_i_2_IBUF_1280 : STD_LOGIC; 
  signal offset_s_cmp_ge0002 : STD_LOGIC; 
  signal B_i_2_IBUF_1282 : STD_LOGIC; 
  signal offset_s_cmp_ge0003 : STD_LOGIC; 
  signal G_i_2_IBUF_1284 : STD_LOGIC; 
  signal max_s_2_0 : STD_LOGIC; 
  signal N97 : STD_LOGIC; 
  signal G_i_1_IBUF_1287 : STD_LOGIC; 
  signal R_i_1_IBUF_1288 : STD_LOGIC; 
  signal B_i_1_IBUF_1289 : STD_LOGIC; 
  signal diff_nominat_s_mux0000_1_0 : STD_LOGIC; 
  signal N61 : STD_LOGIC; 
  signal R_i_4_IBUF_1292 : STD_LOGIC; 
  signal B_i_4_IBUF_1293 : STD_LOGIC; 
  signal G_i_4_IBUF_1294 : STD_LOGIC; 
  signal min_s_4_0 : STD_LOGIC; 
  signal N67 : STD_LOGIC; 
  signal min_s_1_0 : STD_LOGIC; 
  signal N7_0 : STD_LOGIC; 
  signal N23_0 : STD_LOGIC; 
  signal G_i_0_IBUF_1300 : STD_LOGIC; 
  signal R_i_0_IBUF_1301 : STD_LOGIC; 
  signal N37_0 : STD_LOGIC; 
  signal N29_0 : STD_LOGIC; 
  signal N71 : STD_LOGIC; 
  signal R_i_6_IBUF_1305 : STD_LOGIC; 
  signal B_i_6_IBUF_1306 : STD_LOGIC; 
  signal G_i_6_IBUF_1307 : STD_LOGIC; 
  signal max_s_6_0 : STD_LOGIC; 
  signal N33_0 : STD_LOGIC; 
  signal N35_0 : STD_LOGIC; 
  signal N89 : STD_LOGIC; 
  signal G_i_5_IBUF_1312 : STD_LOGIC; 
  signal R_i_5_IBUF_1313 : STD_LOGIC; 
  signal B_i_5_IBUF_1314 : STD_LOGIC; 
  signal diff_nominat_s_mux0000_5_0 : STD_LOGIC; 
  signal N77 : STD_LOGIC; 
  signal R_i_3_IBUF_1317 : STD_LOGIC; 
  signal B_i_3_IBUF_1318 : STD_LOGIC; 
  signal G_i_3_IBUF_1319 : STD_LOGIC; 
  signal max_s_3_0 : STD_LOGIC; 
  signal N95 : STD_LOGIC; 
  signal diff_nominat_s_mux0000_2_0 : STD_LOGIC; 
  signal N59 : STD_LOGIC; 
  signal min_s_5_0 : STD_LOGIC; 
  signal N83 : STD_LOGIC; 
  signal B_i_0_IBUF_1326 : STD_LOGIC; 
  signal max_s_0_0 : STD_LOGIC; 
  signal N65 : STD_LOGIC; 
  signal min_s_2_0 : STD_LOGIC; 
  signal offset_s_0_0 : STD_LOGIC; 
  signal N31_0 : STD_LOGIC; 
  signal N27_0 : STD_LOGIC; 
  signal N87 : STD_LOGIC; 
  signal diff_nominat_s_mux0000_6_0 : STD_LOGIC; 
  signal N75 : STD_LOGIC; 
  signal max_s_4_0 : STD_LOGIC; 
  signal N93 : STD_LOGIC; 
  signal diff_nominat_s_mux0000_3_0 : STD_LOGIC; 
  signal N57 : STD_LOGIC; 
  signal min_s_6_0 : STD_LOGIC; 
  signal N81 : STD_LOGIC; 
  signal max_s_1_0 : STD_LOGIC; 
  signal N99 : STD_LOGIC; 
  signal diff_nominat_s_mux0000_0_0 : STD_LOGIC; 
  signal N63 : STD_LOGIC; 
  signal min_s_3_0 : STD_LOGIC; 
  signal N69 : STD_LOGIC; 
  signal min_s_0_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal Madd_Y_large_s_addsub0000_Madd_lut_0_0 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_7_Q : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_9_Q : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_11_Q : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_13_Q : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal Msub_diff_min_max_s_cy_1_Q : STD_LOGIC; 
  signal Msub_diff_min_max_s_cy_3_Q : STD_LOGIC; 
  signal max_s_5_0 : STD_LOGIC; 
  signal diff_nominat_s_mux0000_4_0 : STD_LOGIC; 
  signal N25_0 : STD_LOGIC; 
  signal diff_nominat_s_mux0000_7_0 : STD_LOGIC; 
  signal Madd_H_bias_s_Madd_cy_1_Q : STD_LOGIC; 
  signal Madd_H_bias_s_Madd_cy_3_Q : STD_LOGIC; 
  signal clk_i_BUFGP : STD_LOGIC; 
  signal N85 : STD_LOGIC; 
  signal N73 : STD_LOGIC; 
  signal N91 : STD_LOGIC; 
  signal N55_pack_1 : STD_LOGIC; 
  signal N79_pack_1 : STD_LOGIC; 
  signal N97_pack_1 : STD_LOGIC; 
  signal N61_pack_1 : STD_LOGIC; 
  signal N67_pack_1 : STD_LOGIC; 
  signal N7 : STD_LOGIC; 
  signal N23 : STD_LOGIC; 
  signal N37 : STD_LOGIC; 
  signal N29 : STD_LOGIC; 
  signal N71_pack_1 : STD_LOGIC; 
  signal N33 : STD_LOGIC; 
  signal N35 : STD_LOGIC; 
  signal N89_pack_1 : STD_LOGIC; 
  signal N77_pack_1 : STD_LOGIC; 
  signal N95_pack_1 : STD_LOGIC; 
  signal N59_pack_1 : STD_LOGIC; 
  signal N83_pack_1 : STD_LOGIC; 
  signal N65_pack_1 : STD_LOGIC; 
  signal N31 : STD_LOGIC; 
  signal N27 : STD_LOGIC; 
  signal N87_pack_1 : STD_LOGIC; 
  signal N75_pack_1 : STD_LOGIC; 
  signal N93_pack_1 : STD_LOGIC; 
  signal N57_pack_1 : STD_LOGIC; 
  signal N81_pack_1 : STD_LOGIC; 
  signal N99_pack_1 : STD_LOGIC; 
  signal N63_pack_1 : STD_LOGIC; 
  signal N69_pack_1 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_1_CYINIT_2150 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_1_CY0F_2149 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_1_CYSELF_2141 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_1_CYMUXG_2138 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_0_Q : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_1_CY0G_2136 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_1_CYSELG_2128 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_3_CY0F_2181 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_3_CYSELF_2172 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_3_CYMUXFAST_2171 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_3_CYAND_2170 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_3_FASTCARRY_2169 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_3_CYMUXG2_2168 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_3_CYMUXF2_2167 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_3_CY0G_2166 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_3_CYSELG_2158 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_5_CY0F_2212 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_5_CYSELF_2203 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_5_CYMUXFAST_2202 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_5_CYAND_2201 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_5_FASTCARRY_2200 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_5_CYMUXG2_2199 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_5_CYMUXF2_2198 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_5_CY0G_2197 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_5_CYSELG_2189 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_7_CY0F_2243 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_7_CYSELF_2234 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_7_CYMUXFAST_2233 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_7_CYAND_2232 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_7_FASTCARRY_2231 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_7_CYMUXG2_2230 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_7_CYMUXF2_2229 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_7_CY0G_2228 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_7_CYSELG_2220 : STD_LOGIC; 
  signal Y_large_s_9_CYINIT_2279 : STD_LOGIC; 
  signal Y_large_s_9_CY0F_2278 : STD_LOGIC; 
  signal Y_large_s_9_XORG_2268 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_8_Q : STD_LOGIC; 
  signal Y_large_s_9_CYSELF_2266 : STD_LOGIC; 
  signal Y_large_s_9_CYMUXFAST_2265 : STD_LOGIC; 
  signal Y_large_s_9_CYAND_2264 : STD_LOGIC; 
  signal Y_large_s_9_FASTCARRY_2263 : STD_LOGIC; 
  signal Y_large_s_9_CYMUXG2_2262 : STD_LOGIC; 
  signal Y_large_s_9_CYMUXF2_2261 : STD_LOGIC; 
  signal Y_large_s_9_CY0G_2260 : STD_LOGIC; 
  signal Y_large_s_9_CYSELG_2252 : STD_LOGIC; 
  signal Y_large_s_10_XORF_2317 : STD_LOGIC; 
  signal Y_large_s_10_CYINIT_2316 : STD_LOGIC; 
  signal Y_large_s_10_CY0F_2315 : STD_LOGIC; 
  signal Y_large_s_10_XORG_2305 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_10_Q : STD_LOGIC; 
  signal Y_large_s_10_CYSELF_2303 : STD_LOGIC; 
  signal Y_large_s_10_CYMUXFAST_2302 : STD_LOGIC; 
  signal Y_large_s_10_CYAND_2301 : STD_LOGIC; 
  signal Y_large_s_10_FASTCARRY_2300 : STD_LOGIC; 
  signal Y_large_s_10_CYMUXG2_2299 : STD_LOGIC; 
  signal Y_large_s_10_CYMUXF2_2298 : STD_LOGIC; 
  signal Y_large_s_10_CY0G_2297 : STD_LOGIC; 
  signal Y_large_s_10_CYSELG_2289 : STD_LOGIC; 
  signal Y_large_s_12_XORF_2356 : STD_LOGIC; 
  signal Y_large_s_12_CYINIT_2355 : STD_LOGIC; 
  signal Y_large_s_12_CY0F_2354 : STD_LOGIC; 
  signal Y_large_s_12_XORG_2344 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_12_Q : STD_LOGIC; 
  signal Y_large_s_12_CYSELF_2342 : STD_LOGIC; 
  signal Y_large_s_12_CYMUXFAST_2341 : STD_LOGIC; 
  signal Y_large_s_12_CYAND_2340 : STD_LOGIC; 
  signal Y_large_s_12_FASTCARRY_2339 : STD_LOGIC; 
  signal Y_large_s_12_CYMUXG2_2338 : STD_LOGIC; 
  signal Y_large_s_12_CYMUXF2_2337 : STD_LOGIC; 
  signal Y_large_s_12_CY0G_2336 : STD_LOGIC; 
  signal Y_large_s_12_CYSELG_2328 : STD_LOGIC; 
  signal Y_large_s_14_XORF_2395 : STD_LOGIC; 
  signal Y_large_s_14_CYINIT_2394 : STD_LOGIC; 
  signal Y_large_s_14_CY0F_2393 : STD_LOGIC; 
  signal Y_large_s_14_XORG_2383 : STD_LOGIC; 
  signal Madd_Y_large_s_Madd_cy_14_Q : STD_LOGIC; 
  signal Y_large_s_14_CYSELF_2381 : STD_LOGIC; 
  signal Y_large_s_14_CYMUXFAST_2380 : STD_LOGIC; 
  signal Y_large_s_14_CYAND_2379 : STD_LOGIC; 
  signal Y_large_s_14_FASTCARRY_2378 : STD_LOGIC; 
  signal Y_large_s_14_CYMUXG2_2377 : STD_LOGIC; 
  signal Y_large_s_14_CYMUXF2_2376 : STD_LOGIC; 
  signal Y_large_s_14_CY0G_2375 : STD_LOGIC; 
  signal Y_large_s_14_CYSELG_2367 : STD_LOGIC; 
  signal Y_large_s_16_XORF_2410 : STD_LOGIC; 
  signal Y_large_s_16_CYINIT_2409 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_1_CYINIT_2441 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_1_CY0F_2440 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_1_CYSELF_2432 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_1_CYMUXG_2429 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_1_CY0G_2427 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_1_CYSELG_2419 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_3_CY0F_2472 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_3_CYSELF_2463 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_3_CYMUXFAST_2462 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_3_CYAND_2461 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_3_FASTCARRY_2460 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_3_CYMUXG2_2459 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_3_CYMUXF2_2458 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_3_CY0G_2457 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_3_CYSELG_2449 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_5_CY0F_2503 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_5_CYSELF_2494 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_5_CYMUXFAST_2493 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_5_CYAND_2492 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_5_FASTCARRY_2491 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_5_CYMUXG2_2490 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_5_CYMUXF2_2489 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_5_CY0G_2488 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0001_cy_5_CYSELG_2480 : STD_LOGIC; 
  signal min_s_cmp_le0001_CY0F_2534 : STD_LOGIC; 
  signal min_s_cmp_le0001_CYSELF_2525 : STD_LOGIC; 
  signal min_s_cmp_le0001_CYMUXFAST_2524 : STD_LOGIC; 
  signal min_s_cmp_le0001_CYAND_2523 : STD_LOGIC; 
  signal min_s_cmp_le0001_FASTCARRY_2522 : STD_LOGIC; 
  signal min_s_cmp_le0001_CYMUXG2_2521 : STD_LOGIC; 
  signal min_s_cmp_le0001_CYMUXF2_2520 : STD_LOGIC; 
  signal min_s_cmp_le0001_CY0G_2519 : STD_LOGIC; 
  signal min_s_cmp_le0001_CYSELG_2511 : STD_LOGIC; 
  signal diff_min_max_s_0_XORF_2569 : STD_LOGIC; 
  signal diff_min_max_s_0_CYINIT_2568 : STD_LOGIC; 
  signal diff_min_max_s_0_CY0F_2567 : STD_LOGIC; 
  signal diff_min_max_s_0_CYSELF_2559 : STD_LOGIC; 
  signal diff_min_max_s_0_XORG_2555 : STD_LOGIC; 
  signal diff_min_max_s_0_CYMUXG_2554 : STD_LOGIC; 
  signal Msub_diff_min_max_s_cy_0_Q : STD_LOGIC; 
  signal diff_min_max_s_0_CY0G_2552 : STD_LOGIC; 
  signal diff_min_max_s_0_CYSELG_2544 : STD_LOGIC; 
  signal diff_min_max_s_2_XORF_2608 : STD_LOGIC; 
  signal diff_min_max_s_2_CYINIT_2607 : STD_LOGIC; 
  signal diff_min_max_s_2_CY0F_2606 : STD_LOGIC; 
  signal diff_min_max_s_2_XORG_2596 : STD_LOGIC; 
  signal Msub_diff_min_max_s_cy_2_Q : STD_LOGIC; 
  signal diff_min_max_s_2_CYSELF_2594 : STD_LOGIC; 
  signal diff_min_max_s_2_CYMUXFAST_2593 : STD_LOGIC; 
  signal diff_min_max_s_2_CYAND_2592 : STD_LOGIC; 
  signal diff_min_max_s_2_FASTCARRY_2591 : STD_LOGIC; 
  signal diff_min_max_s_2_CYMUXG2_2590 : STD_LOGIC; 
  signal diff_min_max_s_2_CYMUXF2_2589 : STD_LOGIC; 
  signal diff_min_max_s_2_CY0G_2588 : STD_LOGIC; 
  signal diff_min_max_s_2_CYSELG_2580 : STD_LOGIC; 
  signal diff_min_max_s_4_XORF_2647 : STD_LOGIC; 
  signal diff_min_max_s_4_CYINIT_2646 : STD_LOGIC; 
  signal diff_min_max_s_4_CY0F_2645 : STD_LOGIC; 
  signal diff_min_max_s_4_XORG_2635 : STD_LOGIC; 
  signal Msub_diff_min_max_s_cy_4_Q : STD_LOGIC; 
  signal diff_min_max_s_4_CYSELF_2633 : STD_LOGIC; 
  signal diff_min_max_s_4_CYMUXFAST_2632 : STD_LOGIC; 
  signal diff_min_max_s_4_CYAND_2631 : STD_LOGIC; 
  signal diff_min_max_s_4_FASTCARRY_2630 : STD_LOGIC; 
  signal diff_min_max_s_4_CYMUXG2_2629 : STD_LOGIC; 
  signal diff_min_max_s_4_CYMUXF2_2628 : STD_LOGIC; 
  signal diff_min_max_s_4_CY0G_2627 : STD_LOGIC; 
  signal diff_min_max_s_4_CYSELG_2619 : STD_LOGIC; 
  signal diff_min_max_s_6_XORF_2678 : STD_LOGIC; 
  signal diff_min_max_s_6_CYINIT_2677 : STD_LOGIC; 
  signal diff_min_max_s_6_CY0F_2676 : STD_LOGIC; 
  signal diff_min_max_s_6_CYSELF_2668 : STD_LOGIC; 
  signal diff_min_max_s_6_XORG_2665 : STD_LOGIC; 
  signal Msub_diff_min_max_s_cy_6_Q : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_1_CYINIT_2709 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_1_CY0F_2708 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_1_CYSELF_2700 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_1_CYMUXG_2697 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_1_CY0G_2695 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_1_CYSELG_2687 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_3_CY0F_2740 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_3_CYSELF_2731 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_3_CYMUXFAST_2730 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_3_CYAND_2729 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_3_FASTCARRY_2728 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_3_CYMUXG2_2727 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_3_CYMUXF2_2726 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_3_CY0G_2725 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_3_CYSELG_2717 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_5_CY0F_2771 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_5_CYSELF_2762 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_5_CYMUXFAST_2761 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_5_CYAND_2760 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_5_FASTCARRY_2759 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_5_CYMUXG2_2758 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_5_CYMUXF2_2757 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_5_CY0G_2756 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0001_cy_5_CYSELG_2748 : STD_LOGIC; 
  signal offset_s_cmp_ge0001_CY0F_2802 : STD_LOGIC; 
  signal offset_s_cmp_ge0001_CYSELF_2793 : STD_LOGIC; 
  signal offset_s_cmp_ge0001_CYMUXFAST_2792 : STD_LOGIC; 
  signal offset_s_cmp_ge0001_CYAND_2791 : STD_LOGIC; 
  signal offset_s_cmp_ge0001_FASTCARRY_2790 : STD_LOGIC; 
  signal offset_s_cmp_ge0001_CYMUXG2_2789 : STD_LOGIC; 
  signal offset_s_cmp_ge0001_CYMUXF2_2788 : STD_LOGIC; 
  signal offset_s_cmp_ge0001_CY0G_2787 : STD_LOGIC; 
  signal offset_s_cmp_ge0001_CYSELG_2779 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_1_CYINIT_2832 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_1_CY0F_2831 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_1_CYSELF_2823 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_1_CYMUXG_2820 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_1_CY0G_2818 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_1_CYSELG_2810 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_3_CY0F_2863 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_3_CYSELF_2854 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_3_CYMUXFAST_2853 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_3_CYAND_2852 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_3_FASTCARRY_2851 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_3_CYMUXG2_2850 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_3_CYMUXF2_2849 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_3_CY0G_2848 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_3_CYSELG_2840 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_5_CY0F_2894 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_5_CYSELF_2885 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_5_CYMUXFAST_2884 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_5_CYAND_2883 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_5_FASTCARRY_2882 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_5_CYMUXG2_2881 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_5_CYMUXF2_2880 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_5_CY0G_2879 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0003_cy_5_CYSELG_2871 : STD_LOGIC; 
  signal min_s_cmp_le0003_CY0F_2925 : STD_LOGIC; 
  signal min_s_cmp_le0003_CYSELF_2916 : STD_LOGIC; 
  signal min_s_cmp_le0003_CYMUXFAST_2915 : STD_LOGIC; 
  signal min_s_cmp_le0003_CYAND_2914 : STD_LOGIC; 
  signal min_s_cmp_le0003_FASTCARRY_2913 : STD_LOGIC; 
  signal min_s_cmp_le0003_CYMUXG2_2912 : STD_LOGIC; 
  signal min_s_cmp_le0003_CYMUXF2_2911 : STD_LOGIC; 
  signal min_s_cmp_le0003_CY0G_2910 : STD_LOGIC; 
  signal min_s_cmp_le0003_CYSELG_2902 : STD_LOGIC; 
  signal diff_nominat_s_0_XORF_2960 : STD_LOGIC; 
  signal diff_nominat_s_0_CYINIT_2959 : STD_LOGIC; 
  signal diff_nominat_s_0_CY0F_2958 : STD_LOGIC; 
  signal diff_nominat_s_0_CYSELF_2952 : STD_LOGIC; 
  signal diff_nominat_s_0_XORG_2948 : STD_LOGIC; 
  signal diff_nominat_s_0_CYMUXG_2947 : STD_LOGIC; 
  signal diff_nominat_s_0_CY0G_2945 : STD_LOGIC; 
  signal diff_nominat_s_0_CYSELG_2939 : STD_LOGIC; 
  signal diff_nominat_s_2_XORF_2999 : STD_LOGIC; 
  signal diff_nominat_s_2_CYINIT_2998 : STD_LOGIC; 
  signal diff_nominat_s_2_CY0F_2997 : STD_LOGIC; 
  signal diff_nominat_s_2_XORG_2989 : STD_LOGIC; 
  signal diff_nominat_s_2_CYSELF_2987 : STD_LOGIC; 
  signal diff_nominat_s_2_CYMUXFAST_2986 : STD_LOGIC; 
  signal diff_nominat_s_2_CYAND_2985 : STD_LOGIC; 
  signal diff_nominat_s_2_FASTCARRY_2984 : STD_LOGIC; 
  signal diff_nominat_s_2_CYMUXG2_2983 : STD_LOGIC; 
  signal diff_nominat_s_2_CYMUXF2_2982 : STD_LOGIC; 
  signal diff_nominat_s_2_CY0G_2981 : STD_LOGIC; 
  signal diff_nominat_s_2_CYSELG_2975 : STD_LOGIC; 
  signal diff_nominat_s_4_XORF_3038 : STD_LOGIC; 
  signal diff_nominat_s_4_CYINIT_3037 : STD_LOGIC; 
  signal diff_nominat_s_4_CY0F_3036 : STD_LOGIC; 
  signal diff_nominat_s_4_XORG_3028 : STD_LOGIC; 
  signal diff_nominat_s_4_CYSELF_3026 : STD_LOGIC; 
  signal diff_nominat_s_4_CYMUXFAST_3025 : STD_LOGIC; 
  signal diff_nominat_s_4_CYAND_3024 : STD_LOGIC; 
  signal diff_nominat_s_4_FASTCARRY_3023 : STD_LOGIC; 
  signal diff_nominat_s_4_CYMUXG2_3022 : STD_LOGIC; 
  signal diff_nominat_s_4_CYMUXF2_3021 : STD_LOGIC; 
  signal diff_nominat_s_4_CY0G_3020 : STD_LOGIC; 
  signal diff_nominat_s_4_CYSELG_3014 : STD_LOGIC; 
  signal diff_nominat_s_6_XORF_3077 : STD_LOGIC; 
  signal diff_nominat_s_6_CYINIT_3076 : STD_LOGIC; 
  signal diff_nominat_s_6_CY0F_3075 : STD_LOGIC; 
  signal diff_nominat_s_6_XORG_3067 : STD_LOGIC; 
  signal diff_nominat_s_6_CYSELF_3065 : STD_LOGIC; 
  signal diff_nominat_s_6_CYMUXFAST_3064 : STD_LOGIC; 
  signal diff_nominat_s_6_CYAND_3063 : STD_LOGIC; 
  signal diff_nominat_s_6_FASTCARRY_3062 : STD_LOGIC; 
  signal diff_nominat_s_6_CYMUXG2_3061 : STD_LOGIC; 
  signal diff_nominat_s_6_CYMUXF2_3060 : STD_LOGIC; 
  signal diff_nominat_s_6_CY0G_3059 : STD_LOGIC; 
  signal diff_nominat_s_6_CYSELG_3053 : STD_LOGIC; 
  signal H_bias_s_0_CYINIT_3127 : STD_LOGIC; 
  signal H_bias_s_0_CY0F_3126 : STD_LOGIC; 
  signal H_bias_s_0_CYSELF_3119 : STD_LOGIC; 
  signal H_bias_s_0_XORG_3115 : STD_LOGIC; 
  signal H_bias_s_0_CYMUXG_3114 : STD_LOGIC; 
  signal Madd_H_bias_s_Madd_cy_0_Q : STD_LOGIC; 
  signal H_bias_s_0_CY0G_3112 : STD_LOGIC; 
  signal H_bias_s_0_CYSELG_3106 : STD_LOGIC; 
  signal H_bias_s_2_XORF_3166 : STD_LOGIC; 
  signal H_bias_s_2_CYINIT_3165 : STD_LOGIC; 
  signal H_bias_s_2_CY0F_3164 : STD_LOGIC; 
  signal H_bias_s_2_XORG_3156 : STD_LOGIC; 
  signal Madd_H_bias_s_Madd_cy_2_Q : STD_LOGIC; 
  signal H_bias_s_2_CYSELF_3154 : STD_LOGIC; 
  signal H_bias_s_2_CYMUXFAST_3153 : STD_LOGIC; 
  signal H_bias_s_2_CYAND_3152 : STD_LOGIC; 
  signal H_bias_s_2_FASTCARRY_3151 : STD_LOGIC; 
  signal H_bias_s_2_CYMUXG2_3150 : STD_LOGIC; 
  signal H_bias_s_2_CYMUXF2_3149 : STD_LOGIC; 
  signal H_bias_s_2_CY0G_3148 : STD_LOGIC; 
  signal H_bias_s_2_CYSELG_3142 : STD_LOGIC; 
  signal H_bias_s_4_XORF_3205 : STD_LOGIC; 
  signal H_bias_s_4_CYINIT_3204 : STD_LOGIC; 
  signal H_bias_s_4_CY0F_3203 : STD_LOGIC; 
  signal H_bias_s_4_XORG_3195 : STD_LOGIC; 
  signal Madd_H_bias_s_Madd_cy_4_Q : STD_LOGIC; 
  signal H_bias_s_4_CYSELF_3193 : STD_LOGIC; 
  signal H_bias_s_4_CYMUXFAST_3192 : STD_LOGIC; 
  signal H_bias_s_4_CYAND_3191 : STD_LOGIC; 
  signal H_bias_s_4_FASTCARRY_3190 : STD_LOGIC; 
  signal H_bias_s_4_CYMUXG2_3189 : STD_LOGIC; 
  signal H_bias_s_4_CYMUXF2_3188 : STD_LOGIC; 
  signal H_bias_s_4_CY0G_3187 : STD_LOGIC; 
  signal H_bias_s_4_CYSELG_3181 : STD_LOGIC; 
  signal H_bias_s_6_XORF_3236 : STD_LOGIC; 
  signal H_bias_s_6_CYINIT_3235 : STD_LOGIC; 
  signal H_bias_s_6_CY0F_3234 : STD_LOGIC; 
  signal H_bias_s_6_CYSELF_3228 : STD_LOGIC; 
  signal H_bias_s_6_XORG_3225 : STD_LOGIC; 
  signal Madd_H_bias_s_Madd_cy_6_Q : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_1_CYINIT_3267 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_1_CY0F_3266 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_1_CYSELF_3258 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_1_CYMUXG_3255 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_1_CY0G_3253 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_1_CYSELG_3245 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_3_CY0F_3298 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_3_CYSELF_3289 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_3_CYMUXFAST_3288 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_3_CYAND_3287 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_3_FASTCARRY_3286 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_3_CYMUXG2_3285 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_3_CYMUXF2_3284 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_3_CY0G_3283 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_3_CYSELG_3275 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_5_CY0F_3329 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_5_CYSELF_3320 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_5_CYMUXFAST_3319 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_5_CYAND_3318 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_5_FASTCARRY_3317 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_5_CYMUXG2_3316 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_5_CYMUXF2_3315 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_5_CY0G_3314 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0000_cy_5_CYSELG_3306 : STD_LOGIC; 
  signal min_s_cmp_le0000_CY0F_3360 : STD_LOGIC; 
  signal min_s_cmp_le0000_CYSELF_3351 : STD_LOGIC; 
  signal min_s_cmp_le0000_CYMUXFAST_3350 : STD_LOGIC; 
  signal min_s_cmp_le0000_CYAND_3349 : STD_LOGIC; 
  signal min_s_cmp_le0000_FASTCARRY_3348 : STD_LOGIC; 
  signal min_s_cmp_le0000_CYMUXG2_3347 : STD_LOGIC; 
  signal min_s_cmp_le0000_CYMUXF2_3346 : STD_LOGIC; 
  signal min_s_cmp_le0000_CY0G_3345 : STD_LOGIC; 
  signal min_s_cmp_le0000_CYSELG_3337 : STD_LOGIC; 
  signal Madd_Y_large_s_addsub0000_Madd_lut_0_CYINIT_3394 : STD_LOGIC; 
  signal Madd_Y_large_s_addsub0000_Madd_lut_0_CY0F_3393 : STD_LOGIC; 
  signal Madd_Y_large_s_addsub0000_Madd_lut_0_CYSELF_3385 : STD_LOGIC; 
  signal Madd_Y_large_s_addsub0000_Madd_lut_0_XORG_3381 : STD_LOGIC; 
  signal Madd_Y_large_s_addsub0000_Madd_lut_0_CYMUXG_3380 : STD_LOGIC; 
  signal Madd_Y_large_s_addsub0000_Madd_lut_0_CY0G_3378 : STD_LOGIC; 
  signal Madd_Y_large_s_addsub0000_Madd_lut_0_CYSELG_3370 : STD_LOGIC; 
  signal Y_large_s_addsub0000_2_XORF_3433 : STD_LOGIC; 
  signal Y_large_s_addsub0000_2_CYINIT_3432 : STD_LOGIC; 
  signal Y_large_s_addsub0000_2_CY0F_3431 : STD_LOGIC; 
  signal Y_large_s_addsub0000_2_XORG_3421 : STD_LOGIC; 
  signal Y_large_s_addsub0000_2_CYSELF_3419 : STD_LOGIC; 
  signal Y_large_s_addsub0000_2_CYMUXFAST_3418 : STD_LOGIC; 
  signal Y_large_s_addsub0000_2_CYAND_3417 : STD_LOGIC; 
  signal Y_large_s_addsub0000_2_FASTCARRY_3416 : STD_LOGIC; 
  signal Y_large_s_addsub0000_2_CYMUXG2_3415 : STD_LOGIC; 
  signal Y_large_s_addsub0000_2_CYMUXF2_3414 : STD_LOGIC; 
  signal Y_large_s_addsub0000_2_CY0G_3413 : STD_LOGIC; 
  signal Y_large_s_addsub0000_2_CYSELG_3405 : STD_LOGIC; 
  signal Y_large_s_addsub0000_4_XORF_3472 : STD_LOGIC; 
  signal Y_large_s_addsub0000_4_CYINIT_3471 : STD_LOGIC; 
  signal Y_large_s_addsub0000_4_CY0F_3470 : STD_LOGIC; 
  signal Y_large_s_addsub0000_4_XORG_3460 : STD_LOGIC; 
  signal Y_large_s_addsub0000_4_CYSELF_3458 : STD_LOGIC; 
  signal Y_large_s_addsub0000_4_CYMUXFAST_3457 : STD_LOGIC; 
  signal Y_large_s_addsub0000_4_CYAND_3456 : STD_LOGIC; 
  signal Y_large_s_addsub0000_4_FASTCARRY_3455 : STD_LOGIC; 
  signal Y_large_s_addsub0000_4_CYMUXG2_3454 : STD_LOGIC; 
  signal Y_large_s_addsub0000_4_CYMUXF2_3453 : STD_LOGIC; 
  signal Y_large_s_addsub0000_4_CY0G_3452 : STD_LOGIC; 
  signal Y_large_s_addsub0000_4_CYSELG_3444 : STD_LOGIC; 
  signal Y_large_s_addsub0000_6_XORF_3511 : STD_LOGIC; 
  signal Y_large_s_addsub0000_6_CYINIT_3510 : STD_LOGIC; 
  signal Y_large_s_addsub0000_6_CY0F_3509 : STD_LOGIC; 
  signal Y_large_s_addsub0000_6_XORG_3499 : STD_LOGIC; 
  signal Y_large_s_addsub0000_6_CYSELF_3497 : STD_LOGIC; 
  signal Y_large_s_addsub0000_6_CYMUXFAST_3496 : STD_LOGIC; 
  signal Y_large_s_addsub0000_6_CYAND_3495 : STD_LOGIC; 
  signal Y_large_s_addsub0000_6_FASTCARRY_3494 : STD_LOGIC; 
  signal Y_large_s_addsub0000_6_CYMUXG2_3493 : STD_LOGIC; 
  signal Y_large_s_addsub0000_6_CYMUXF2_3492 : STD_LOGIC; 
  signal Y_large_s_addsub0000_6_CY0G_3491 : STD_LOGIC; 
  signal Y_large_s_addsub0000_6_CYSELG_3483 : STD_LOGIC; 
  signal Y_large_s_addsub0000_8_XORF_3550 : STD_LOGIC; 
  signal Y_large_s_addsub0000_8_CYINIT_3549 : STD_LOGIC; 
  signal Y_large_s_addsub0000_8_CY0F_3548 : STD_LOGIC; 
  signal Y_large_s_addsub0000_8_XORG_3538 : STD_LOGIC; 
  signal Y_large_s_addsub0000_8_CYSELF_3536 : STD_LOGIC; 
  signal Y_large_s_addsub0000_8_CYMUXFAST_3535 : STD_LOGIC; 
  signal Y_large_s_addsub0000_8_CYAND_3534 : STD_LOGIC; 
  signal Y_large_s_addsub0000_8_FASTCARRY_3533 : STD_LOGIC; 
  signal Y_large_s_addsub0000_8_CYMUXG2_3532 : STD_LOGIC; 
  signal Y_large_s_addsub0000_8_CYMUXF2_3531 : STD_LOGIC; 
  signal Y_large_s_addsub0000_8_CY0G_3530 : STD_LOGIC; 
  signal Y_large_s_addsub0000_8_CYSELG_3522 : STD_LOGIC; 
  signal Y_large_s_addsub0000_10_XORF_3589 : STD_LOGIC; 
  signal Y_large_s_addsub0000_10_CYINIT_3588 : STD_LOGIC; 
  signal Y_large_s_addsub0000_10_CY0F_3587 : STD_LOGIC; 
  signal Y_large_s_addsub0000_10_XORG_3577 : STD_LOGIC; 
  signal Y_large_s_addsub0000_10_CYSELF_3575 : STD_LOGIC; 
  signal Y_large_s_addsub0000_10_CYMUXFAST_3574 : STD_LOGIC; 
  signal Y_large_s_addsub0000_10_CYAND_3573 : STD_LOGIC; 
  signal Y_large_s_addsub0000_10_FASTCARRY_3572 : STD_LOGIC; 
  signal Y_large_s_addsub0000_10_CYMUXG2_3571 : STD_LOGIC; 
  signal Y_large_s_addsub0000_10_CYMUXF2_3570 : STD_LOGIC; 
  signal Y_large_s_addsub0000_10_CY0G_3569 : STD_LOGIC; 
  signal Y_large_s_addsub0000_10_CYSELG_3561 : STD_LOGIC; 
  signal Y_large_s_addsub0000_12_XORF_3628 : STD_LOGIC; 
  signal Y_large_s_addsub0000_12_CYINIT_3627 : STD_LOGIC; 
  signal Y_large_s_addsub0000_12_CY0F_3626 : STD_LOGIC; 
  signal Y_large_s_addsub0000_12_XORG_3616 : STD_LOGIC; 
  signal Y_large_s_addsub0000_12_CYSELF_3614 : STD_LOGIC; 
  signal Y_large_s_addsub0000_12_CYMUXFAST_3613 : STD_LOGIC; 
  signal Y_large_s_addsub0000_12_CYAND_3612 : STD_LOGIC; 
  signal Y_large_s_addsub0000_12_FASTCARRY_3611 : STD_LOGIC; 
  signal Y_large_s_addsub0000_12_CYMUXG2_3610 : STD_LOGIC; 
  signal Y_large_s_addsub0000_12_CYMUXF2_3609 : STD_LOGIC; 
  signal Y_large_s_addsub0000_12_CY0G_3608 : STD_LOGIC; 
  signal Y_large_s_addsub0000_12_CYSELG_3600 : STD_LOGIC; 
  signal Y_large_s_addsub0000_14_XORF_3667 : STD_LOGIC; 
  signal Y_large_s_addsub0000_14_CYINIT_3666 : STD_LOGIC; 
  signal Y_large_s_addsub0000_14_CY0F_3665 : STD_LOGIC; 
  signal Y_large_s_addsub0000_14_XORG_3655 : STD_LOGIC; 
  signal Y_large_s_addsub0000_14_CYSELF_3653 : STD_LOGIC; 
  signal Y_large_s_addsub0000_14_CYMUXFAST_3652 : STD_LOGIC; 
  signal Y_large_s_addsub0000_14_CYAND_3651 : STD_LOGIC; 
  signal Y_large_s_addsub0000_14_FASTCARRY_3650 : STD_LOGIC; 
  signal Y_large_s_addsub0000_14_CYMUXG2_3649 : STD_LOGIC; 
  signal Y_large_s_addsub0000_14_CYMUXF2_3648 : STD_LOGIC; 
  signal Y_large_s_addsub0000_14_CY0G_3647 : STD_LOGIC; 
  signal Y_large_s_addsub0000_14_CYSELG_3639 : STD_LOGIC; 
  signal Y_large_s_addsub0000_16_XORF_3682 : STD_LOGIC; 
  signal Y_large_s_addsub0000_16_CYINIT_3681 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_1_CYINIT_3713 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_1_CY0F_3712 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_1_CYSELF_3704 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_1_CYMUXG_3701 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_1_CY0G_3699 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_1_CYSELG_3691 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_3_CY0F_3744 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_3_CYSELF_3735 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_3_CYMUXFAST_3734 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_3_CYAND_3733 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_3_FASTCARRY_3732 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_3_CYMUXG2_3731 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_3_CYMUXF2_3730 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_3_CY0G_3729 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_3_CYSELG_3721 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_5_CY0F_3775 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_5_CYSELF_3766 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_5_CYMUXFAST_3765 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_5_CYAND_3764 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_5_FASTCARRY_3763 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_5_CYMUXG2_3762 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_5_CYMUXF2_3761 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_5_CY0G_3760 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0003_cy_5_CYSELG_3752 : STD_LOGIC; 
  signal offset_s_cmp_ge0003_CY0F_3806 : STD_LOGIC; 
  signal offset_s_cmp_ge0003_CYSELF_3797 : STD_LOGIC; 
  signal offset_s_cmp_ge0003_CYMUXFAST_3796 : STD_LOGIC; 
  signal offset_s_cmp_ge0003_CYAND_3795 : STD_LOGIC; 
  signal offset_s_cmp_ge0003_FASTCARRY_3794 : STD_LOGIC; 
  signal offset_s_cmp_ge0003_CYMUXG2_3793 : STD_LOGIC; 
  signal offset_s_cmp_ge0003_CYMUXF2_3792 : STD_LOGIC; 
  signal offset_s_cmp_ge0003_CY0G_3791 : STD_LOGIC; 
  signal offset_s_cmp_ge0003_CYSELG_3783 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_1_CYINIT_3836 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_1_CY0F_3835 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_1_CYSELF_3827 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_1_CYMUXG_3824 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_1_CY0G_3822 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_1_CYSELG_3814 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_3_CY0F_3867 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_3_CYSELF_3858 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_3_CYMUXFAST_3857 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_3_CYAND_3856 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_3_FASTCARRY_3855 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_3_CYMUXG2_3854 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_3_CYMUXF2_3853 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_3_CY0G_3852 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_3_CYSELG_3844 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_5_CY0F_3898 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_5_CYSELF_3889 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_5_CYMUXFAST_3888 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_5_CYAND_3887 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_5_FASTCARRY_3886 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_5_CYMUXG2_3885 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_5_CYMUXF2_3884 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_5_CY0G_3883 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0000_cy_5_CYSELG_3875 : STD_LOGIC; 
  signal offset_s_cmp_ge0000_CY0F_3929 : STD_LOGIC; 
  signal offset_s_cmp_ge0000_CYSELF_3920 : STD_LOGIC; 
  signal offset_s_cmp_ge0000_CYMUXFAST_3919 : STD_LOGIC; 
  signal offset_s_cmp_ge0000_CYAND_3918 : STD_LOGIC; 
  signal offset_s_cmp_ge0000_FASTCARRY_3917 : STD_LOGIC; 
  signal offset_s_cmp_ge0000_CYMUXG2_3916 : STD_LOGIC; 
  signal offset_s_cmp_ge0000_CYMUXF2_3915 : STD_LOGIC; 
  signal offset_s_cmp_ge0000_CY0G_3914 : STD_LOGIC; 
  signal offset_s_cmp_ge0000_CYSELG_3906 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_1_CYINIT_3959 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_1_CY0F_3958 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_1_CYSELF_3950 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_1_CYMUXG_3947 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_1_CY0G_3945 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_1_CYSELG_3937 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_3_CY0F_3990 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_3_CYSELF_3981 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_3_CYMUXFAST_3980 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_3_CYAND_3979 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_3_FASTCARRY_3978 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_3_CYMUXG2_3977 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_3_CYMUXF2_3976 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_3_CY0G_3975 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_3_CYSELG_3967 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_5_CY0F_4021 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_5_CYSELF_4012 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_5_CYMUXFAST_4011 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_5_CYAND_4010 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_5_FASTCARRY_4009 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_5_CYMUXG2_4008 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_5_CYMUXF2_4007 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_5_CY0G_4006 : STD_LOGIC; 
  signal Mcompar_min_s_cmp_le0002_cy_5_CYSELG_3998 : STD_LOGIC; 
  signal min_s_cmp_le0002_CY0F_4052 : STD_LOGIC; 
  signal min_s_cmp_le0002_CYSELF_4043 : STD_LOGIC; 
  signal min_s_cmp_le0002_CYMUXFAST_4042 : STD_LOGIC; 
  signal min_s_cmp_le0002_CYAND_4041 : STD_LOGIC; 
  signal min_s_cmp_le0002_FASTCARRY_4040 : STD_LOGIC; 
  signal min_s_cmp_le0002_CYMUXG2_4039 : STD_LOGIC; 
  signal min_s_cmp_le0002_CYMUXF2_4038 : STD_LOGIC; 
  signal min_s_cmp_le0002_CY0G_4037 : STD_LOGIC; 
  signal min_s_cmp_le0002_CYSELG_4029 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_1_CYINIT_4082 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_1_CY0F_4081 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_1_CYSELF_4073 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_1_CYMUXG_4070 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_1_CY0G_4068 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_1_CYSELG_4060 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_3_CY0F_4113 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_3_CYSELF_4104 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_3_CYMUXFAST_4103 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_3_CYAND_4102 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_3_FASTCARRY_4101 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_3_CYMUXG2_4100 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_3_CYMUXF2_4099 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_3_CY0G_4098 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_3_CYSELG_4090 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_5_CY0F_4144 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_5_CYSELF_4135 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_5_CYMUXFAST_4134 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_5_CYAND_4133 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_5_FASTCARRY_4132 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_5_CYMUXG2_4131 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_5_CYMUXF2_4130 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_5_CY0G_4129 : STD_LOGIC; 
  signal Mcompar_offset_s_cmp_ge0002_cy_5_CYSELG_4121 : STD_LOGIC; 
  signal offset_s_cmp_ge0002_CY0F_4175 : STD_LOGIC; 
  signal offset_s_cmp_ge0002_CYSELF_4166 : STD_LOGIC; 
  signal offset_s_cmp_ge0002_CYMUXFAST_4165 : STD_LOGIC; 
  signal offset_s_cmp_ge0002_CYAND_4164 : STD_LOGIC; 
  signal offset_s_cmp_ge0002_FASTCARRY_4163 : STD_LOGIC; 
  signal offset_s_cmp_ge0002_CYMUXG2_4162 : STD_LOGIC; 
  signal offset_s_cmp_ge0002_CYMUXF2_4161 : STD_LOGIC; 
  signal offset_s_cmp_ge0002_CY0G_4160 : STD_LOGIC; 
  signal offset_s_cmp_ge0002_CYSELG_4152 : STD_LOGIC; 
  signal Y_o_1_O : STD_LOGIC; 
  signal Y_o_2_O : STD_LOGIC; 
  signal Y_o_3_O : STD_LOGIC; 
  signal Y_o_4_O : STD_LOGIC; 
  signal Y_o_5_O : STD_LOGIC; 
  signal Y_o_6_O : STD_LOGIC; 
  signal Y_o_7_O : STD_LOGIC; 
  signal B_i_0_INBUF : STD_LOGIC; 
  signal B_i_1_INBUF : STD_LOGIC; 
  signal B_i_2_INBUF : STD_LOGIC; 
  signal B_i_3_INBUF : STD_LOGIC; 
  signal R_i_0_INBUF : STD_LOGIC; 
  signal B_i_4_INBUF : STD_LOGIC; 
  signal R_i_1_INBUF : STD_LOGIC; 
  signal B_i_5_INBUF : STD_LOGIC; 
  signal R_i_2_INBUF : STD_LOGIC; 
  signal B_i_6_INBUF : STD_LOGIC; 
  signal R_i_3_INBUF : STD_LOGIC; 
  signal B_i_7_INBUF : STD_LOGIC; 
  signal R_i_4_INBUF : STD_LOGIC; 
  signal R_i_5_INBUF : STD_LOGIC; 
  signal clk_i_INBUF : STD_LOGIC; 
  signal R_i_6_INBUF : STD_LOGIC; 
  signal R_i_7_INBUF : STD_LOGIC; 
  signal H_o_0_O : STD_LOGIC; 
  signal H_o_1_O : STD_LOGIC; 
  signal H_o_2_O : STD_LOGIC; 
  signal H_o_3_O : STD_LOGIC; 
  signal H_o_4_O : STD_LOGIC; 
  signal H_o_5_O : STD_LOGIC; 
  signal H_o_6_O : STD_LOGIC; 
  signal H_o_7_O : STD_LOGIC; 
  signal G_i_0_INBUF : STD_LOGIC; 
  signal G_i_1_INBUF : STD_LOGIC; 
  signal G_i_2_INBUF : STD_LOGIC; 
  signal G_i_3_INBUF : STD_LOGIC; 
  signal G_i_4_INBUF : STD_LOGIC; 
  signal G_i_5_INBUF : STD_LOGIC; 
  signal G_i_6_INBUF : STD_LOGIC; 
  signal G_i_7_INBUF : STD_LOGIC; 
  signal Y_o_0_O : STD_LOGIC; 
  signal clk_i_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal clk_i_BUFGP_BUFG_I0_INV : STD_LOGIC; 
  signal Mmult_G_output_s_PROD17 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD18 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD19 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD20 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD21 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD22 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD23 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD24 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD25 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD26 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD27 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD28 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD29 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD30 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD31 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD32 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD33 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD34 : STD_LOGIC; 
  signal Mmult_G_output_s_PROD35 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD0 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD1 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD2 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD3 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD4 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD5 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD6 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD7 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD8 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD17 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD18 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD19 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD20 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD21 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD22 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD23 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD24 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD25 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD26 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD27 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD28 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD29 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD30 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD31 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD32 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD33 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD34 : STD_LOGIC; 
  signal Mmult_H_large_s_PROD35 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD15 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD16 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD17 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD18 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD19 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD20 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD21 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD22 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD23 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD24 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD25 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD26 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD27 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD28 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD29 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD30 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD31 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD32 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD33 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD34 : STD_LOGIC; 
  signal Mmult_B_output_s_PROD35 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD17 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD18 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD19 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD20 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD21 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD22 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD23 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD24 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD25 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD26 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD27 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD28 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD29 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD30 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD31 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD32 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD33 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD34 : STD_LOGIC; 
  signal Mmult_R_output_s_PROD35 : STD_LOGIC; 
  signal RAMB16_S18_inst_DOPA1 : STD_LOGIC; 
  signal RAMB16_S18_inst_DOPA0 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIPA1 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIPA0 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIA15 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIA14 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIA13 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIA12 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIA11 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIA10 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIA9 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIA8 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIA7 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIA6 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIA5 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIA4 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIA3 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIA2 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIA1 : STD_LOGIC; 
  signal RAMB16_S18_inst_DIA0 : STD_LOGIC; 
  signal N25 : STD_LOGIC; 
  signal N85_pack_1 : STD_LOGIC; 
  signal N73_pack_1 : STD_LOGIC; 
  signal N91_pack_1 : STD_LOGIC; 
  signal diff_nominat_s_8_XORF_3092 : STD_LOGIC; 
  signal diff_nominat_s_8_CYINIT_3091 : STD_LOGIC; 
  signal diff_nominat_s_8_F : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal B_output_s : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal Y_large_s_addsub0000 : STD_LOGIC_VECTOR ( 16 downto 1 ); 
  signal diff_min_max_s : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal diff_nominat_s : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal Msub_diff_nominat_s_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal H_large_s : STD_LOGIC_VECTOR ( 16 downto 9 ); 
  signal R_output_s : STD_LOGIC_VECTOR ( 16 downto 0 ); 
  signal G_output_s : STD_LOGIC_VECTOR ( 16 downto 0 ); 
  signal Madd_Y_large_s_addsub0000_Madd_cy : STD_LOGIC_VECTOR ( 14 downto 0 ); 
  signal RAM_out_s : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal min_s : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal max_s : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal diff_nominat_s_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal offset_s : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Madd_Y_large_s_Madd_lut : STD_LOGIC_VECTOR ( 16 downto 0 ); 
  signal Mcompar_min_s_cmp_le0001_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Mcompar_min_s_cmp_le0001_cy : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Msub_diff_min_max_s_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Mcompar_offset_s_cmp_ge0001_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Mcompar_offset_s_cmp_ge0001_cy : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcompar_min_s_cmp_le0003_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Mcompar_min_s_cmp_le0003_cy : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Msub_diff_nominat_s_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal H_bias_s : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Madd_H_bias_s_Madd_lut : STD_LOGIC_VECTOR ( 7 downto 1 ); 
  signal Mcompar_min_s_cmp_le0000_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Mcompar_min_s_cmp_le0000_cy : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Madd_Y_large_s_addsub0000_Madd_lut : STD_LOGIC_VECTOR ( 16 downto 0 ); 
  signal Mcompar_offset_s_cmp_ge0003_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Mcompar_offset_s_cmp_ge0003_cy : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcompar_offset_s_cmp_ge0000_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Mcompar_offset_s_cmp_ge0000_cy : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcompar_min_s_cmp_le0002_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Mcompar_min_s_cmp_le0002_cy : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal Mcompar_offset_s_cmp_ge0002_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Mcompar_offset_s_cmp_ge0002_cy : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  min_s_7_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X31Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => min_s(7),
      O => min_s_7_0
    );
  min_s_7_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X31Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => N55_pack_1,
      O => N55
    );
  min_s_7_SW0 : X_LUT4
    generic map(
      INIT => X"5333",
      LOC => "SLICE_X31Y25"
    )
    port map (
      ADR0 => G_i_7_IBUF_1275,
      ADR1 => B_i_7_IBUF_1273,
      ADR2 => min_s_cmp_le0003,
      ADR3 => min_s_cmp_le0002,
      O => N55_pack_1
    );
  max_s_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => max_s(2),
      O => max_s_2_0
    );
  max_s_2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => N79_pack_1,
      O => N79
    );
  max_s_2_SW1 : X_LUT4
    generic map(
      INIT => X"078F",
      LOC => "SLICE_X26Y25"
    )
    port map (
      ADR0 => offset_s_cmp_ge0003,
      ADR1 => offset_s_cmp_ge0002,
      ADR2 => B_i_2_IBUF_1282,
      ADR3 => G_i_2_IBUF_1284,
      O => N79_pack_1
    );
  diff_nominat_s_mux0000_1_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_mux0000(1),
      O => diff_nominat_s_mux0000_1_0
    );
  diff_nominat_s_mux0000_1_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => N97_pack_1,
      O => N97
    );
  diff_nominat_s_mux0000_1_SW1 : X_LUT4
    generic map(
      INIT => X"D8F0",
      LOC => "SLICE_X25Y23"
    )
    port map (
      ADR0 => offset_s_cmp_ge0002,
      ADR1 => B_i_1_IBUF_1289,
      ADR2 => R_i_1_IBUF_1288,
      ADR3 => offset_s_cmp_ge0003,
      O => N97_pack_1
    );
  min_s_4_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => min_s(4),
      O => min_s_4_0
    );
  min_s_4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => N61_pack_1,
      O => N61
    );
  min_s_4_SW0 : X_LUT4
    generic map(
      INIT => X"1D55",
      LOC => "SLICE_X30Y24"
    )
    port map (
      ADR0 => B_i_4_IBUF_1293,
      ADR1 => min_s_cmp_le0002,
      ADR2 => G_i_4_IBUF_1294,
      ADR3 => min_s_cmp_le0003,
      O => N61_pack_1
    );
  min_s_1_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X31Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => min_s(1),
      O => min_s_1_0
    );
  min_s_1_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X31Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => N67_pack_1,
      O => N67
    );
  min_s_1_SW0 : X_LUT4
    generic map(
      INIT => X"207F",
      LOC => "SLICE_X31Y23"
    )
    port map (
      ADR0 => min_s_cmp_le0002,
      ADR1 => G_i_1_IBUF_1287,
      ADR2 => min_s_cmp_le0003,
      ADR3 => B_i_1_IBUF_1289,
      O => N67_pack_1
    );
  N7_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => N7,
      O => N7_0
    );
  N7_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => N23,
      O => N23_0
    );
  diff_nominat_s_mux0001_7_SW0 : X_LUT4
    generic map(
      INIT => X"BF80",
      LOC => "SLICE_X24Y23"
    )
    port map (
      ADR0 => R_i_7_IBUF_1271,
      ADR1 => offset_s_cmp_ge0002,
      ADR2 => offset_s_cmp_ge0003,
      ADR3 => G_i_7_IBUF_1275,
      O => N23
    );
  N37_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => N37,
      O => N37_0
    );
  N37_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => N29,
      O => N29_0
    );
  diff_nominat_s_mux0001_4_SW0 : X_LUT4
    generic map(
      INIT => X"F780",
      LOC => "SLICE_X23Y23"
    )
    port map (
      ADR0 => offset_s_cmp_ge0002,
      ADR1 => offset_s_cmp_ge0003,
      ADR2 => R_i_4_IBUF_1292,
      ADR3 => G_i_4_IBUF_1294,
      O => N29
    );
  max_s_6_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => max_s(6),
      O => max_s_6_0
    );
  max_s_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => N71_pack_1,
      O => N71
    );
  max_s_6_SW1 : X_LUT4
    generic map(
      INIT => X"270F",
      LOC => "SLICE_X29Y24"
    )
    port map (
      ADR0 => offset_s_cmp_ge0003,
      ADR1 => G_i_6_IBUF_1307,
      ADR2 => B_i_6_IBUF_1306,
      ADR3 => offset_s_cmp_ge0002,
      O => N71_pack_1
    );
  N33_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => N33,
      O => N33_0
    );
  N33_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => N35,
      O => N35_0
    );
  diff_nominat_s_mux0001_1_SW0 : X_LUT4
    generic map(
      INIT => X"F870",
      LOC => "SLICE_X24Y20"
    )
    port map (
      ADR0 => offset_s_cmp_ge0003,
      ADR1 => offset_s_cmp_ge0002,
      ADR2 => G_i_1_IBUF_1287,
      ADR3 => R_i_1_IBUF_1288,
      O => N35
    );
  diff_nominat_s_mux0000_5_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_mux0000(5),
      O => diff_nominat_s_mux0000_5_0
    );
  diff_nominat_s_mux0000_5_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => N89_pack_1,
      O => N89
    );
  diff_nominat_s_mux0000_5_SW1 : X_LUT4
    generic map(
      INIT => X"D8F0",
      LOC => "SLICE_X25Y25"
    )
    port map (
      ADR0 => offset_s_cmp_ge0002,
      ADR1 => B_i_5_IBUF_1314,
      ADR2 => R_i_5_IBUF_1313,
      ADR3 => offset_s_cmp_ge0003,
      O => N89_pack_1
    );
  max_s_3_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => max_s(3),
      O => max_s_3_0
    );
  max_s_3_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => N77_pack_1,
      O => N77
    );
  max_s_3_SW1 : X_LUT4
    generic map(
      INIT => X"3555",
      LOC => "SLICE_X26Y24"
    )
    port map (
      ADR0 => B_i_3_IBUF_1318,
      ADR1 => G_i_3_IBUF_1319,
      ADR2 => offset_s_cmp_ge0003,
      ADR3 => offset_s_cmp_ge0002,
      O => N77_pack_1
    );
  diff_nominat_s_mux0000_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_mux0000(2),
      O => diff_nominat_s_mux0000_2_0
    );
  diff_nominat_s_mux0000_2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => N95_pack_1,
      O => N95
    );
  diff_nominat_s_mux0000_2_SW1 : X_LUT4
    generic map(
      INIT => X"F870",
      LOC => "SLICE_X25Y21"
    )
    port map (
      ADR0 => offset_s_cmp_ge0002,
      ADR1 => offset_s_cmp_ge0003,
      ADR2 => R_i_2_IBUF_1280,
      ADR3 => B_i_2_IBUF_1282,
      O => N95_pack_1
    );
  min_s_5_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => min_s(5),
      O => min_s_5_0
    );
  min_s_5_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => N59_pack_1,
      O => N59
    );
  min_s_5_SW0 : X_LUT4
    generic map(
      INIT => X"1B33",
      LOC => "SLICE_X28Y24"
    )
    port map (
      ADR0 => min_s_cmp_le0002,
      ADR1 => B_i_5_IBUF_1314,
      ADR2 => G_i_5_IBUF_1312,
      ADR3 => min_s_cmp_le0003,
      O => N59_pack_1
    );
  max_s_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => max_s(0),
      O => max_s_0_0
    );
  max_s_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => N83_pack_1,
      O => N83
    );
  max_s_0_SW1 : X_LUT4
    generic map(
      INIT => X"13B3",
      LOC => "SLICE_X26Y22"
    )
    port map (
      ADR0 => offset_s_cmp_ge0002,
      ADR1 => B_i_0_IBUF_1326,
      ADR2 => offset_s_cmp_ge0003,
      ADR3 => G_i_0_IBUF_1300,
      O => N83_pack_1
    );
  min_s_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X31Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => min_s(2),
      O => min_s_2_0
    );
  min_s_2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X31Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => N65_pack_1,
      O => N65
    );
  min_s_2_SW0 : X_LUT4
    generic map(
      INIT => X"13B3",
      LOC => "SLICE_X31Y22"
    )
    port map (
      ADR0 => min_s_cmp_le0003,
      ADR1 => B_i_2_IBUF_1282,
      ADR2 => min_s_cmp_le0002,
      ADR3 => G_i_2_IBUF_1284,
      O => N65_pack_1
    );
  offset_s_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => offset_s(0),
      O => offset_s_0_0
    );
  offset_s_0_1 : X_LUT4
    generic map(
      INIT => X"7777",
      LOC => "SLICE_X16Y25"
    )
    port map (
      ADR0 => offset_s_cmp_ge0001,
      ADR1 => offset_s_cmp_ge0000,
      ADR2 => VCC,
      ADR3 => VCC,
      O => offset_s(0)
    );
  N31_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => N31,
      O => N31_0
    );
  N31_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => N27,
      O => N27_0
    );
  diff_nominat_s_mux0001_5_SW0 : X_LUT4
    generic map(
      INIT => X"F780",
      LOC => "SLICE_X25Y22"
    )
    port map (
      ADR0 => offset_s_cmp_ge0002,
      ADR1 => offset_s_cmp_ge0003,
      ADR2 => R_i_5_IBUF_1313,
      ADR3 => G_i_5_IBUF_1312,
      O => N27
    );
  diff_nominat_s_mux0000_6_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_mux0000(6),
      O => diff_nominat_s_mux0000_6_0
    );
  diff_nominat_s_mux0000_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => N87_pack_1,
      O => N87
    );
  diff_nominat_s_mux0000_6_SW1 : X_LUT4
    generic map(
      INIT => X"D8F0",
      LOC => "SLICE_X28Y23"
    )
    port map (
      ADR0 => offset_s_cmp_ge0003,
      ADR1 => B_i_6_IBUF_1306,
      ADR2 => R_i_6_IBUF_1305,
      ADR3 => offset_s_cmp_ge0002,
      O => N87_pack_1
    );
  max_s_4_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => max_s(4),
      O => max_s_4_0
    );
  max_s_4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => N75_pack_1,
      O => N75
    );
  max_s_4_SW1 : X_LUT4
    generic map(
      INIT => X"270F",
      LOC => "SLICE_X25Y24"
    )
    port map (
      ADR0 => offset_s_cmp_ge0002,
      ADR1 => G_i_4_IBUF_1294,
      ADR2 => B_i_4_IBUF_1293,
      ADR3 => offset_s_cmp_ge0003,
      O => N75_pack_1
    );
  diff_nominat_s_mux0000_3_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_mux0000(3),
      O => diff_nominat_s_mux0000_3_0
    );
  diff_nominat_s_mux0000_3_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => N93_pack_1,
      O => N93
    );
  diff_nominat_s_mux0000_3_SW1 : X_LUT4
    generic map(
      INIT => X"F870",
      LOC => "SLICE_X25Y20"
    )
    port map (
      ADR0 => offset_s_cmp_ge0002,
      ADR1 => offset_s_cmp_ge0003,
      ADR2 => R_i_3_IBUF_1317,
      ADR3 => B_i_3_IBUF_1318,
      O => N93_pack_1
    );
  min_s_6_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X31Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => min_s(6),
      O => min_s_6_0
    );
  min_s_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X31Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => N57_pack_1,
      O => N57
    );
  min_s_6_SW0 : X_LUT4
    generic map(
      INIT => X"270F",
      LOC => "SLICE_X31Y24"
    )
    port map (
      ADR0 => min_s_cmp_le0003,
      ADR1 => G_i_6_IBUF_1307,
      ADR2 => B_i_6_IBUF_1306,
      ADR3 => min_s_cmp_le0002,
      O => N57_pack_1
    );
  max_s_1_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => max_s(1),
      O => max_s_1_0
    );
  max_s_1_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => N81_pack_1,
      O => N81
    );
  max_s_1_SW1 : X_LUT4
    generic map(
      INIT => X"270F",
      LOC => "SLICE_X29Y23"
    )
    port map (
      ADR0 => offset_s_cmp_ge0002,
      ADR1 => G_i_1_IBUF_1287,
      ADR2 => B_i_1_IBUF_1289,
      ADR3 => offset_s_cmp_ge0003,
      O => N81_pack_1
    );
  diff_nominat_s_mux0000_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_mux0000(0),
      O => diff_nominat_s_mux0000_0_0
    );
  diff_nominat_s_mux0000_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => N99_pack_1,
      O => N99
    );
  diff_nominat_s_mux0000_0_SW1 : X_LUT4
    generic map(
      INIT => X"B8F0",
      LOC => "SLICE_X26Y23"
    )
    port map (
      ADR0 => B_i_0_IBUF_1326,
      ADR1 => offset_s_cmp_ge0003,
      ADR2 => R_i_0_IBUF_1301,
      ADR3 => offset_s_cmp_ge0002,
      O => N99_pack_1
    );
  min_s_3_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => min_s(3),
      O => min_s_3_0
    );
  min_s_3_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => N63_pack_1,
      O => N63
    );
  min_s_3_SW0 : X_LUT4
    generic map(
      INIT => X"1B33",
      LOC => "SLICE_X30Y22"
    )
    port map (
      ADR0 => min_s_cmp_le0002,
      ADR1 => B_i_3_IBUF_1318,
      ADR2 => G_i_3_IBUF_1319,
      ADR3 => min_s_cmp_le0003,
      O => N63_pack_1
    );
  min_s_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => min_s(0),
      O => min_s_0_0
    );
  min_s_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => N69_pack_1,
      O => N69
    );
  min_s_0_SW0 : X_LUT4
    generic map(
      INIT => X"078F",
      LOC => "SLICE_X30Y23"
    )
    port map (
      ADR0 => min_s_cmp_le0003,
      ADR1 => min_s_cmp_le0002,
      ADR2 => B_i_0_IBUF_1326,
      ADR3 => G_i_0_IBUF_1300,
      O => N69_pack_1
    );
  Madd_Y_large_s_Madd_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X35Y20"
    )
    port map (
      IA => Madd_Y_large_s_Madd_cy_1_CY0F_2149,
      IB => Madd_Y_large_s_Madd_cy_1_CYINIT_2150,
      SEL => Madd_Y_large_s_Madd_cy_1_CYSELF_2141,
      O => Madd_Y_large_s_Madd_cy_0_Q
    );
  Madd_Y_large_s_Madd_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X35Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => Madd_Y_large_s_Madd_cy_1_CYINIT_2150
    );
  Madd_Y_large_s_Madd_cy_1_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X35Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut_0_0,
      O => Madd_Y_large_s_Madd_cy_1_CY0F_2149
    );
  Madd_Y_large_s_Madd_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X35Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_lut(0),
      O => Madd_Y_large_s_Madd_cy_1_CYSELF_2141
    );
  Madd_Y_large_s_Madd_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X35Y20"
    )
    port map (
      IA => Madd_Y_large_s_Madd_cy_1_CY0G_2136,
      IB => Madd_Y_large_s_Madd_cy_0_Q,
      SEL => Madd_Y_large_s_Madd_cy_1_CYSELG_2128,
      O => Madd_Y_large_s_Madd_cy_1_CYMUXG_2138
    );
  Madd_Y_large_s_Madd_cy_1_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X35Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000(1),
      O => Madd_Y_large_s_Madd_cy_1_CY0G_2136
    );
  Madd_Y_large_s_Madd_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X35Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_lut(1),
      O => Madd_Y_large_s_Madd_cy_1_CYSELG_2128
    );
  Madd_Y_large_s_Madd_lut_1_Q : X_LUT4
    generic map(
      INIT => X"55AA",
      LOC => "SLICE_X35Y20"
    )
    port map (
      ADR0 => Y_large_s_addsub0000(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => B_output_s(1),
      O => Madd_Y_large_s_Madd_lut(1)
    );
  Madd_Y_large_s_Madd_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y21"
    )
    port map (
      IA => Madd_Y_large_s_Madd_cy_3_CY0F_2181,
      IB => Madd_Y_large_s_Madd_cy_3_CY0F_2181,
      SEL => Madd_Y_large_s_Madd_cy_3_CYSELF_2172,
      O => Madd_Y_large_s_Madd_cy_3_CYMUXF2_2167
    );
  Madd_Y_large_s_Madd_cy_3_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X35Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000(2),
      O => Madd_Y_large_s_Madd_cy_3_CY0F_2181
    );
  Madd_Y_large_s_Madd_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X35Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_lut(2),
      O => Madd_Y_large_s_Madd_cy_3_CYSELF_2172
    );
  Madd_Y_large_s_Madd_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X35Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_cy_1_CYMUXG_2138,
      O => Madd_Y_large_s_Madd_cy_3_FASTCARRY_2169
    );
  Madd_Y_large_s_Madd_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X35Y21"
    )
    port map (
      I0 => Madd_Y_large_s_Madd_cy_3_CYSELG_2158,
      I1 => Madd_Y_large_s_Madd_cy_3_CYSELF_2172,
      O => Madd_Y_large_s_Madd_cy_3_CYAND_2170
    );
  Madd_Y_large_s_Madd_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X35Y21"
    )
    port map (
      IA => Madd_Y_large_s_Madd_cy_3_CYMUXG2_2168,
      IB => Madd_Y_large_s_Madd_cy_3_FASTCARRY_2169,
      SEL => Madd_Y_large_s_Madd_cy_3_CYAND_2170,
      O => Madd_Y_large_s_Madd_cy_3_CYMUXFAST_2171
    );
  Madd_Y_large_s_Madd_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y21"
    )
    port map (
      IA => Madd_Y_large_s_Madd_cy_3_CY0G_2166,
      IB => Madd_Y_large_s_Madd_cy_3_CYMUXF2_2167,
      SEL => Madd_Y_large_s_Madd_cy_3_CYSELG_2158,
      O => Madd_Y_large_s_Madd_cy_3_CYMUXG2_2168
    );
  Madd_Y_large_s_Madd_cy_3_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X35Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000(3),
      O => Madd_Y_large_s_Madd_cy_3_CY0G_2166
    );
  Madd_Y_large_s_Madd_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X35Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_lut(3),
      O => Madd_Y_large_s_Madd_cy_3_CYSELG_2158
    );
  Madd_Y_large_s_Madd_lut_3_Q : X_LUT4
    generic map(
      INIT => X"3C3C",
      LOC => "SLICE_X35Y21"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Y_large_s_addsub0000(3),
      ADR2 => B_output_s(3),
      ADR3 => VCC,
      O => Madd_Y_large_s_Madd_lut(3)
    );
  Madd_Y_large_s_Madd_cy_5_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y22"
    )
    port map (
      IA => Madd_Y_large_s_Madd_cy_5_CY0F_2212,
      IB => Madd_Y_large_s_Madd_cy_5_CY0F_2212,
      SEL => Madd_Y_large_s_Madd_cy_5_CYSELF_2203,
      O => Madd_Y_large_s_Madd_cy_5_CYMUXF2_2198
    );
  Madd_Y_large_s_Madd_cy_5_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X35Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000(4),
      O => Madd_Y_large_s_Madd_cy_5_CY0F_2212
    );
  Madd_Y_large_s_Madd_cy_5_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X35Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_lut(4),
      O => Madd_Y_large_s_Madd_cy_5_CYSELF_2203
    );
  Madd_Y_large_s_Madd_cy_5_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X35Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_cy_3_CYMUXFAST_2171,
      O => Madd_Y_large_s_Madd_cy_5_FASTCARRY_2200
    );
  Madd_Y_large_s_Madd_cy_5_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X35Y22"
    )
    port map (
      I0 => Madd_Y_large_s_Madd_cy_5_CYSELG_2189,
      I1 => Madd_Y_large_s_Madd_cy_5_CYSELF_2203,
      O => Madd_Y_large_s_Madd_cy_5_CYAND_2201
    );
  Madd_Y_large_s_Madd_cy_5_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X35Y22"
    )
    port map (
      IA => Madd_Y_large_s_Madd_cy_5_CYMUXG2_2199,
      IB => Madd_Y_large_s_Madd_cy_5_FASTCARRY_2200,
      SEL => Madd_Y_large_s_Madd_cy_5_CYAND_2201,
      O => Madd_Y_large_s_Madd_cy_5_CYMUXFAST_2202
    );
  Madd_Y_large_s_Madd_cy_5_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y22"
    )
    port map (
      IA => Madd_Y_large_s_Madd_cy_5_CY0G_2197,
      IB => Madd_Y_large_s_Madd_cy_5_CYMUXF2_2198,
      SEL => Madd_Y_large_s_Madd_cy_5_CYSELG_2189,
      O => Madd_Y_large_s_Madd_cy_5_CYMUXG2_2199
    );
  Madd_Y_large_s_Madd_cy_5_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X35Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000(5),
      O => Madd_Y_large_s_Madd_cy_5_CY0G_2197
    );
  Madd_Y_large_s_Madd_cy_5_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X35Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_lut(5),
      O => Madd_Y_large_s_Madd_cy_5_CYSELG_2189
    );
  Madd_Y_large_s_Madd_lut_5_Q : X_LUT4
    generic map(
      INIT => X"6666",
      LOC => "SLICE_X35Y22"
    )
    port map (
      ADR0 => Y_large_s_addsub0000(5),
      ADR1 => B_output_s(5),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Madd_Y_large_s_Madd_lut(5)
    );
  Madd_Y_large_s_Madd_cy_7_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y23"
    )
    port map (
      IA => Madd_Y_large_s_Madd_cy_7_CY0F_2243,
      IB => Madd_Y_large_s_Madd_cy_7_CY0F_2243,
      SEL => Madd_Y_large_s_Madd_cy_7_CYSELF_2234,
      O => Madd_Y_large_s_Madd_cy_7_CYMUXF2_2229
    );
  Madd_Y_large_s_Madd_cy_7_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X35Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000(6),
      O => Madd_Y_large_s_Madd_cy_7_CY0F_2243
    );
  Madd_Y_large_s_Madd_cy_7_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X35Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_lut(6),
      O => Madd_Y_large_s_Madd_cy_7_CYSELF_2234
    );
  Madd_Y_large_s_Madd_cy_7_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X35Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_cy_7_CYMUXFAST_2233,
      O => Madd_Y_large_s_Madd_cy_7_Q
    );
  Madd_Y_large_s_Madd_cy_7_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X35Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_cy_5_CYMUXFAST_2202,
      O => Madd_Y_large_s_Madd_cy_7_FASTCARRY_2231
    );
  Madd_Y_large_s_Madd_cy_7_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X35Y23"
    )
    port map (
      I0 => Madd_Y_large_s_Madd_cy_7_CYSELG_2220,
      I1 => Madd_Y_large_s_Madd_cy_7_CYSELF_2234,
      O => Madd_Y_large_s_Madd_cy_7_CYAND_2232
    );
  Madd_Y_large_s_Madd_cy_7_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X35Y23"
    )
    port map (
      IA => Madd_Y_large_s_Madd_cy_7_CYMUXG2_2230,
      IB => Madd_Y_large_s_Madd_cy_7_FASTCARRY_2231,
      SEL => Madd_Y_large_s_Madd_cy_7_CYAND_2232,
      O => Madd_Y_large_s_Madd_cy_7_CYMUXFAST_2233
    );
  Madd_Y_large_s_Madd_cy_7_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y23"
    )
    port map (
      IA => Madd_Y_large_s_Madd_cy_7_CY0G_2228,
      IB => Madd_Y_large_s_Madd_cy_7_CYMUXF2_2229,
      SEL => Madd_Y_large_s_Madd_cy_7_CYSELG_2220,
      O => Madd_Y_large_s_Madd_cy_7_CYMUXG2_2230
    );
  Madd_Y_large_s_Madd_cy_7_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X35Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000(7),
      O => Madd_Y_large_s_Madd_cy_7_CY0G_2228
    );
  Madd_Y_large_s_Madd_cy_7_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X35Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_lut(7),
      O => Madd_Y_large_s_Madd_cy_7_CYSELG_2220
    );
  Madd_Y_large_s_Madd_lut_7_Q : X_LUT4
    generic map(
      INIT => X"33CC",
      LOC => "SLICE_X35Y23"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Y_large_s_addsub0000(7),
      ADR2 => VCC,
      ADR3 => B_output_s(7),
      O => Madd_Y_large_s_Madd_lut(7)
    );
  Y_large_s_9_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X35Y24"
    )
    port map (
      IA => Y_large_s_9_CY0F_2278,
      IB => Y_large_s_9_CYINIT_2279,
      SEL => Y_large_s_9_CYSELF_2266,
      O => Madd_Y_large_s_Madd_cy_8_Q
    );
  Y_large_s_9_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y24"
    )
    port map (
      IA => Y_large_s_9_CY0F_2278,
      IB => Y_large_s_9_CY0F_2278,
      SEL => Y_large_s_9_CYSELF_2266,
      O => Y_large_s_9_CYMUXF2_2261
    );
  Y_large_s_9_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X35Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_cy_7_Q,
      O => Y_large_s_9_CYINIT_2279
    );
  Y_large_s_9_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X35Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000(8),
      O => Y_large_s_9_CY0F_2278
    );
  Y_large_s_9_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X35Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_lut(8),
      O => Y_large_s_9_CYSELF_2266
    );
  Y_large_s_9_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X35Y24"
    )
    port map (
      I0 => Madd_Y_large_s_Madd_cy_8_Q,
      I1 => Madd_Y_large_s_Madd_lut(9),
      O => Y_large_s_9_XORG_2268
    );
  Y_large_s_9_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X35Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_9_CYMUXFAST_2265,
      O => Madd_Y_large_s_Madd_cy_9_Q
    );
  Y_large_s_9_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X35Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_cy_7_Q,
      O => Y_large_s_9_FASTCARRY_2263
    );
  Y_large_s_9_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X35Y24"
    )
    port map (
      I0 => Y_large_s_9_CYSELG_2252,
      I1 => Y_large_s_9_CYSELF_2266,
      O => Y_large_s_9_CYAND_2264
    );
  Y_large_s_9_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X35Y24"
    )
    port map (
      IA => Y_large_s_9_CYMUXG2_2262,
      IB => Y_large_s_9_FASTCARRY_2263,
      SEL => Y_large_s_9_CYAND_2264,
      O => Y_large_s_9_CYMUXFAST_2265
    );
  Y_large_s_9_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y24"
    )
    port map (
      IA => Y_large_s_9_CY0G_2260,
      IB => Y_large_s_9_CYMUXF2_2261,
      SEL => Y_large_s_9_CYSELG_2252,
      O => Y_large_s_9_CYMUXG2_2262
    );
  Y_large_s_9_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X35Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000(9),
      O => Y_large_s_9_CY0G_2260
    );
  Y_large_s_9_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X35Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_lut(9),
      O => Y_large_s_9_CYSELG_2252
    );
  Madd_Y_large_s_Madd_lut_9_Q : X_LUT4
    generic map(
      INIT => X"6666",
      LOC => "SLICE_X35Y24"
    )
    port map (
      ADR0 => Y_large_s_addsub0000(9),
      ADR1 => B_output_s(9),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Madd_Y_large_s_Madd_lut(9)
    );
  Y_large_s_10_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X35Y25"
    )
    port map (
      I0 => Y_large_s_10_CYINIT_2316,
      I1 => Madd_Y_large_s_Madd_lut(10),
      O => Y_large_s_10_XORF_2317
    );
  Y_large_s_10_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X35Y25"
    )
    port map (
      IA => Y_large_s_10_CY0F_2315,
      IB => Y_large_s_10_CYINIT_2316,
      SEL => Y_large_s_10_CYSELF_2303,
      O => Madd_Y_large_s_Madd_cy_10_Q
    );
  Y_large_s_10_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y25"
    )
    port map (
      IA => Y_large_s_10_CY0F_2315,
      IB => Y_large_s_10_CY0F_2315,
      SEL => Y_large_s_10_CYSELF_2303,
      O => Y_large_s_10_CYMUXF2_2298
    );
  Y_large_s_10_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X35Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_cy_9_Q,
      O => Y_large_s_10_CYINIT_2316
    );
  Y_large_s_10_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X35Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000(10),
      O => Y_large_s_10_CY0F_2315
    );
  Y_large_s_10_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X35Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_lut(10),
      O => Y_large_s_10_CYSELF_2303
    );
  Y_large_s_10_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X35Y25"
    )
    port map (
      I0 => Madd_Y_large_s_Madd_cy_10_Q,
      I1 => Madd_Y_large_s_Madd_lut(11),
      O => Y_large_s_10_XORG_2305
    );
  Y_large_s_10_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X35Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_10_CYMUXFAST_2302,
      O => Madd_Y_large_s_Madd_cy_11_Q
    );
  Y_large_s_10_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X35Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_cy_9_Q,
      O => Y_large_s_10_FASTCARRY_2300
    );
  Y_large_s_10_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X35Y25"
    )
    port map (
      I0 => Y_large_s_10_CYSELG_2289,
      I1 => Y_large_s_10_CYSELF_2303,
      O => Y_large_s_10_CYAND_2301
    );
  Y_large_s_10_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X35Y25"
    )
    port map (
      IA => Y_large_s_10_CYMUXG2_2299,
      IB => Y_large_s_10_FASTCARRY_2300,
      SEL => Y_large_s_10_CYAND_2301,
      O => Y_large_s_10_CYMUXFAST_2302
    );
  Y_large_s_10_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y25"
    )
    port map (
      IA => Y_large_s_10_CY0G_2297,
      IB => Y_large_s_10_CYMUXF2_2298,
      SEL => Y_large_s_10_CYSELG_2289,
      O => Y_large_s_10_CYMUXG2_2299
    );
  Y_large_s_10_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X35Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000(11),
      O => Y_large_s_10_CY0G_2297
    );
  Y_large_s_10_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X35Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_lut(11),
      O => Y_large_s_10_CYSELG_2289
    );
  Madd_Y_large_s_Madd_lut_11_Q : X_LUT4
    generic map(
      INIT => X"3C3C",
      LOC => "SLICE_X35Y25"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Y_large_s_addsub0000(11),
      ADR2 => B_output_s(11),
      ADR3 => VCC,
      O => Madd_Y_large_s_Madd_lut(11)
    );
  Y_large_s_12_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X35Y26"
    )
    port map (
      I0 => Y_large_s_12_CYINIT_2355,
      I1 => Madd_Y_large_s_Madd_lut(12),
      O => Y_large_s_12_XORF_2356
    );
  Y_large_s_12_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X35Y26"
    )
    port map (
      IA => Y_large_s_12_CY0F_2354,
      IB => Y_large_s_12_CYINIT_2355,
      SEL => Y_large_s_12_CYSELF_2342,
      O => Madd_Y_large_s_Madd_cy_12_Q
    );
  Y_large_s_12_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y26"
    )
    port map (
      IA => Y_large_s_12_CY0F_2354,
      IB => Y_large_s_12_CY0F_2354,
      SEL => Y_large_s_12_CYSELF_2342,
      O => Y_large_s_12_CYMUXF2_2337
    );
  Y_large_s_12_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X35Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_cy_11_Q,
      O => Y_large_s_12_CYINIT_2355
    );
  Y_large_s_12_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X35Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000(12),
      O => Y_large_s_12_CY0F_2354
    );
  Y_large_s_12_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X35Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_lut(12),
      O => Y_large_s_12_CYSELF_2342
    );
  Y_large_s_12_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X35Y26"
    )
    port map (
      I0 => Madd_Y_large_s_Madd_cy_12_Q,
      I1 => Madd_Y_large_s_Madd_lut(13),
      O => Y_large_s_12_XORG_2344
    );
  Y_large_s_12_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X35Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_12_CYMUXFAST_2341,
      O => Madd_Y_large_s_Madd_cy_13_Q
    );
  Y_large_s_12_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X35Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_cy_11_Q,
      O => Y_large_s_12_FASTCARRY_2339
    );
  Y_large_s_12_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X35Y26"
    )
    port map (
      I0 => Y_large_s_12_CYSELG_2328,
      I1 => Y_large_s_12_CYSELF_2342,
      O => Y_large_s_12_CYAND_2340
    );
  Y_large_s_12_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X35Y26"
    )
    port map (
      IA => Y_large_s_12_CYMUXG2_2338,
      IB => Y_large_s_12_FASTCARRY_2339,
      SEL => Y_large_s_12_CYAND_2340,
      O => Y_large_s_12_CYMUXFAST_2341
    );
  Y_large_s_12_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y26"
    )
    port map (
      IA => Y_large_s_12_CY0G_2336,
      IB => Y_large_s_12_CYMUXF2_2337,
      SEL => Y_large_s_12_CYSELG_2328,
      O => Y_large_s_12_CYMUXG2_2338
    );
  Y_large_s_12_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X35Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000(13),
      O => Y_large_s_12_CY0G_2336
    );
  Y_large_s_12_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X35Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_lut(13),
      O => Y_large_s_12_CYSELG_2328
    );
  Madd_Y_large_s_Madd_lut_13_Q : X_LUT4
    generic map(
      INIT => X"55AA",
      LOC => "SLICE_X35Y26"
    )
    port map (
      ADR0 => Y_large_s_addsub0000(13),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => B_output_s(13),
      O => Madd_Y_large_s_Madd_lut(13)
    );
  Y_large_s_14_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X35Y27"
    )
    port map (
      I0 => Y_large_s_14_CYINIT_2394,
      I1 => Madd_Y_large_s_Madd_lut(14),
      O => Y_large_s_14_XORF_2395
    );
  Y_large_s_14_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X35Y27"
    )
    port map (
      IA => Y_large_s_14_CY0F_2393,
      IB => Y_large_s_14_CYINIT_2394,
      SEL => Y_large_s_14_CYSELF_2381,
      O => Madd_Y_large_s_Madd_cy_14_Q
    );
  Y_large_s_14_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y27"
    )
    port map (
      IA => Y_large_s_14_CY0F_2393,
      IB => Y_large_s_14_CY0F_2393,
      SEL => Y_large_s_14_CYSELF_2381,
      O => Y_large_s_14_CYMUXF2_2376
    );
  Y_large_s_14_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X35Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_cy_13_Q,
      O => Y_large_s_14_CYINIT_2394
    );
  Y_large_s_14_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X35Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000(14),
      O => Y_large_s_14_CY0F_2393
    );
  Y_large_s_14_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X35Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_lut(14),
      O => Y_large_s_14_CYSELF_2381
    );
  Y_large_s_14_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X35Y27"
    )
    port map (
      I0 => Madd_Y_large_s_Madd_cy_14_Q,
      I1 => Madd_Y_large_s_Madd_lut(15),
      O => Y_large_s_14_XORG_2383
    );
  Y_large_s_14_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X35Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_cy_13_Q,
      O => Y_large_s_14_FASTCARRY_2378
    );
  Y_large_s_14_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X35Y27"
    )
    port map (
      I0 => Y_large_s_14_CYSELG_2367,
      I1 => Y_large_s_14_CYSELF_2381,
      O => Y_large_s_14_CYAND_2379
    );
  Y_large_s_14_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X35Y27"
    )
    port map (
      IA => Y_large_s_14_CYMUXG2_2377,
      IB => Y_large_s_14_FASTCARRY_2378,
      SEL => Y_large_s_14_CYAND_2379,
      O => Y_large_s_14_CYMUXFAST_2380
    );
  Y_large_s_14_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y27"
    )
    port map (
      IA => Y_large_s_14_CY0G_2375,
      IB => Y_large_s_14_CYMUXF2_2376,
      SEL => Y_large_s_14_CYSELG_2367,
      O => Y_large_s_14_CYMUXG2_2377
    );
  Y_large_s_14_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X35Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000(15),
      O => Y_large_s_14_CY0G_2375
    );
  Y_large_s_14_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X35Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_Madd_lut(15),
      O => Y_large_s_14_CYSELG_2367
    );
  Madd_Y_large_s_Madd_lut_15_Q : X_LUT4
    generic map(
      INIT => X"3C3C",
      LOC => "SLICE_X35Y27"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Y_large_s_addsub0000(15),
      ADR2 => B_output_s(14),
      ADR3 => VCC,
      O => Madd_Y_large_s_Madd_lut(15)
    );
  Y_large_s_16_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X35Y28"
    )
    port map (
      I0 => Y_large_s_16_CYINIT_2409,
      I1 => Madd_Y_large_s_Madd_lut(16),
      O => Y_large_s_16_XORF_2410
    );
  Y_large_s_16_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X35Y28",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_14_CYMUXFAST_2380,
      O => Y_large_s_16_CYINIT_2409
    );
  Madd_Y_large_s_Madd_lut_16_Q : X_LUT4
    generic map(
      INIT => X"33CC",
      LOC => "SLICE_X35Y28"
    )
    port map (
      ADR0 => VCC,
      ADR1 => B_output_s(14),
      ADR2 => VCC,
      ADR3 => Y_large_s_addsub0000(16),
      O => Madd_Y_large_s_Madd_lut(16)
    );
  Mcompar_min_s_cmp_le0001_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X39Y24"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0001_cy_1_CY0F_2440,
      IB => Mcompar_min_s_cmp_le0001_cy_1_CYINIT_2441,
      SEL => Mcompar_min_s_cmp_le0001_cy_1_CYSELF_2432,
      O => Mcompar_min_s_cmp_le0001_cy(0)
    );
  Mcompar_min_s_cmp_le0001_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X39Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => Mcompar_min_s_cmp_le0001_cy_1_CYINIT_2441
    );
  Mcompar_min_s_cmp_le0001_cy_1_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X39Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_0_IBUF_1326,
      O => Mcompar_min_s_cmp_le0001_cy_1_CY0F_2440
    );
  Mcompar_min_s_cmp_le0001_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X39Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0001_lut(0),
      O => Mcompar_min_s_cmp_le0001_cy_1_CYSELF_2432
    );
  Mcompar_min_s_cmp_le0001_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X39Y24"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0001_cy_1_CY0G_2427,
      IB => Mcompar_min_s_cmp_le0001_cy(0),
      SEL => Mcompar_min_s_cmp_le0001_cy_1_CYSELG_2419,
      O => Mcompar_min_s_cmp_le0001_cy_1_CYMUXG_2429
    );
  Mcompar_min_s_cmp_le0001_cy_1_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X39Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_1_IBUF_1289,
      O => Mcompar_min_s_cmp_le0001_cy_1_CY0G_2427
    );
  Mcompar_min_s_cmp_le0001_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X39Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0001_lut(1),
      O => Mcompar_min_s_cmp_le0001_cy_1_CYSELG_2419
    );
  Mcompar_min_s_cmp_le0001_lut_1_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X39Y24"
    )
    port map (
      ADR0 => R_i_1_IBUF_1288,
      ADR1 => B_i_1_IBUF_1289,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0001_lut(1)
    );
  Mcompar_min_s_cmp_le0001_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X39Y25"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0001_cy_3_CY0F_2472,
      IB => Mcompar_min_s_cmp_le0001_cy_3_CY0F_2472,
      SEL => Mcompar_min_s_cmp_le0001_cy_3_CYSELF_2463,
      O => Mcompar_min_s_cmp_le0001_cy_3_CYMUXF2_2458
    );
  Mcompar_min_s_cmp_le0001_cy_3_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X39Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_2_IBUF_1282,
      O => Mcompar_min_s_cmp_le0001_cy_3_CY0F_2472
    );
  Mcompar_min_s_cmp_le0001_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X39Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0001_lut(2),
      O => Mcompar_min_s_cmp_le0001_cy_3_CYSELF_2463
    );
  Mcompar_min_s_cmp_le0001_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X39Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0001_cy_1_CYMUXG_2429,
      O => Mcompar_min_s_cmp_le0001_cy_3_FASTCARRY_2460
    );
  Mcompar_min_s_cmp_le0001_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X39Y25"
    )
    port map (
      I0 => Mcompar_min_s_cmp_le0001_cy_3_CYSELG_2449,
      I1 => Mcompar_min_s_cmp_le0001_cy_3_CYSELF_2463,
      O => Mcompar_min_s_cmp_le0001_cy_3_CYAND_2461
    );
  Mcompar_min_s_cmp_le0001_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X39Y25"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0001_cy_3_CYMUXG2_2459,
      IB => Mcompar_min_s_cmp_le0001_cy_3_FASTCARRY_2460,
      SEL => Mcompar_min_s_cmp_le0001_cy_3_CYAND_2461,
      O => Mcompar_min_s_cmp_le0001_cy_3_CYMUXFAST_2462
    );
  Mcompar_min_s_cmp_le0001_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X39Y25"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0001_cy_3_CY0G_2457,
      IB => Mcompar_min_s_cmp_le0001_cy_3_CYMUXF2_2458,
      SEL => Mcompar_min_s_cmp_le0001_cy_3_CYSELG_2449,
      O => Mcompar_min_s_cmp_le0001_cy_3_CYMUXG2_2459
    );
  Mcompar_min_s_cmp_le0001_cy_3_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X39Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_3_IBUF_1318,
      O => Mcompar_min_s_cmp_le0001_cy_3_CY0G_2457
    );
  Mcompar_min_s_cmp_le0001_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X39Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0001_lut(3),
      O => Mcompar_min_s_cmp_le0001_cy_3_CYSELG_2449
    );
  Mcompar_min_s_cmp_le0001_lut_3_Q : X_LUT4
    generic map(
      INIT => X"A5A5",
      LOC => "SLICE_X39Y25"
    )
    port map (
      ADR0 => B_i_3_IBUF_1318,
      ADR1 => VCC,
      ADR2 => R_i_3_IBUF_1317,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0001_lut(3)
    );
  Mcompar_min_s_cmp_le0001_cy_5_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X39Y26"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0001_cy_5_CY0F_2503,
      IB => Mcompar_min_s_cmp_le0001_cy_5_CY0F_2503,
      SEL => Mcompar_min_s_cmp_le0001_cy_5_CYSELF_2494,
      O => Mcompar_min_s_cmp_le0001_cy_5_CYMUXF2_2489
    );
  Mcompar_min_s_cmp_le0001_cy_5_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X39Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_4_IBUF_1293,
      O => Mcompar_min_s_cmp_le0001_cy_5_CY0F_2503
    );
  Mcompar_min_s_cmp_le0001_cy_5_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X39Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0001_lut(4),
      O => Mcompar_min_s_cmp_le0001_cy_5_CYSELF_2494
    );
  Mcompar_min_s_cmp_le0001_cy_5_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X39Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0001_cy_3_CYMUXFAST_2462,
      O => Mcompar_min_s_cmp_le0001_cy_5_FASTCARRY_2491
    );
  Mcompar_min_s_cmp_le0001_cy_5_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X39Y26"
    )
    port map (
      I0 => Mcompar_min_s_cmp_le0001_cy_5_CYSELG_2480,
      I1 => Mcompar_min_s_cmp_le0001_cy_5_CYSELF_2494,
      O => Mcompar_min_s_cmp_le0001_cy_5_CYAND_2492
    );
  Mcompar_min_s_cmp_le0001_cy_5_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X39Y26"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0001_cy_5_CYMUXG2_2490,
      IB => Mcompar_min_s_cmp_le0001_cy_5_FASTCARRY_2491,
      SEL => Mcompar_min_s_cmp_le0001_cy_5_CYAND_2492,
      O => Mcompar_min_s_cmp_le0001_cy_5_CYMUXFAST_2493
    );
  Mcompar_min_s_cmp_le0001_cy_5_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X39Y26"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0001_cy_5_CY0G_2488,
      IB => Mcompar_min_s_cmp_le0001_cy_5_CYMUXF2_2489,
      SEL => Mcompar_min_s_cmp_le0001_cy_5_CYSELG_2480,
      O => Mcompar_min_s_cmp_le0001_cy_5_CYMUXG2_2490
    );
  Mcompar_min_s_cmp_le0001_cy_5_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X39Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_5_IBUF_1314,
      O => Mcompar_min_s_cmp_le0001_cy_5_CY0G_2488
    );
  Mcompar_min_s_cmp_le0001_cy_5_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X39Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0001_lut(5),
      O => Mcompar_min_s_cmp_le0001_cy_5_CYSELG_2480
    );
  Mcompar_min_s_cmp_le0001_lut_5_Q : X_LUT4
    generic map(
      INIT => X"CC33",
      LOC => "SLICE_X39Y26"
    )
    port map (
      ADR0 => VCC,
      ADR1 => B_i_5_IBUF_1314,
      ADR2 => VCC,
      ADR3 => R_i_5_IBUF_1313,
      O => Mcompar_min_s_cmp_le0001_lut(5)
    );
  min_s_cmp_le0001_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X39Y27"
    )
    port map (
      IA => min_s_cmp_le0001_CY0F_2534,
      IB => min_s_cmp_le0001_CY0F_2534,
      SEL => min_s_cmp_le0001_CYSELF_2525,
      O => min_s_cmp_le0001_CYMUXF2_2520
    );
  min_s_cmp_le0001_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X39Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_6_IBUF_1306,
      O => min_s_cmp_le0001_CY0F_2534
    );
  min_s_cmp_le0001_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X39Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0001_lut(6),
      O => min_s_cmp_le0001_CYSELF_2525
    );
  min_s_cmp_le0001_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X39Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => min_s_cmp_le0001_CYMUXFAST_2524,
      O => min_s_cmp_le0001
    );
  min_s_cmp_le0001_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X39Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0001_cy_5_CYMUXFAST_2493,
      O => min_s_cmp_le0001_FASTCARRY_2522
    );
  min_s_cmp_le0001_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X39Y27"
    )
    port map (
      I0 => min_s_cmp_le0001_CYSELG_2511,
      I1 => min_s_cmp_le0001_CYSELF_2525,
      O => min_s_cmp_le0001_CYAND_2523
    );
  min_s_cmp_le0001_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X39Y27"
    )
    port map (
      IA => min_s_cmp_le0001_CYMUXG2_2521,
      IB => min_s_cmp_le0001_FASTCARRY_2522,
      SEL => min_s_cmp_le0001_CYAND_2523,
      O => min_s_cmp_le0001_CYMUXFAST_2524
    );
  min_s_cmp_le0001_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X39Y27"
    )
    port map (
      IA => min_s_cmp_le0001_CY0G_2519,
      IB => min_s_cmp_le0001_CYMUXF2_2520,
      SEL => min_s_cmp_le0001_CYSELG_2511,
      O => min_s_cmp_le0001_CYMUXG2_2521
    );
  min_s_cmp_le0001_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X39Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_7_IBUF_1273,
      O => min_s_cmp_le0001_CY0G_2519
    );
  min_s_cmp_le0001_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X39Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0001_lut(7),
      O => min_s_cmp_le0001_CYSELG_2511
    );
  Mcompar_min_s_cmp_le0001_lut_7_Q : X_LUT4
    generic map(
      INIT => X"C3C3",
      LOC => "SLICE_X39Y27"
    )
    port map (
      ADR0 => VCC,
      ADR1 => B_i_7_IBUF_1273,
      ADR2 => R_i_7_IBUF_1271,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0001_lut(7)
    );
  diff_min_max_s_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_min_max_s_0_XORF_2569,
      O => diff_min_max_s(0)
    );
  diff_min_max_s_0_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X27Y22"
    )
    port map (
      I0 => diff_min_max_s_0_CYINIT_2568,
      I1 => Msub_diff_min_max_s_lut(0),
      O => diff_min_max_s_0_XORF_2569
    );
  diff_min_max_s_0_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X27Y22"
    )
    port map (
      IA => diff_min_max_s_0_CY0F_2567,
      IB => diff_min_max_s_0_CYINIT_2568,
      SEL => diff_min_max_s_0_CYSELF_2559,
      O => Msub_diff_min_max_s_cy_0_Q
    );
  diff_min_max_s_0_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X27Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => diff_min_max_s_0_CYINIT_2568
    );
  diff_min_max_s_0_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X27Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => max_s_0_0,
      O => diff_min_max_s_0_CY0F_2567
    );
  diff_min_max_s_0_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X27Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_min_max_s_lut(0),
      O => diff_min_max_s_0_CYSELF_2559
    );
  diff_min_max_s_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_min_max_s_0_XORG_2555,
      O => diff_min_max_s(1)
    );
  diff_min_max_s_0_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X27Y22"
    )
    port map (
      I0 => Msub_diff_min_max_s_cy_0_Q,
      I1 => Msub_diff_min_max_s_lut(1),
      O => diff_min_max_s_0_XORG_2555
    );
  diff_min_max_s_0_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_min_max_s_0_CYMUXG_2554,
      O => Msub_diff_min_max_s_cy_1_Q
    );
  diff_min_max_s_0_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X27Y22"
    )
    port map (
      IA => diff_min_max_s_0_CY0G_2552,
      IB => Msub_diff_min_max_s_cy_0_Q,
      SEL => diff_min_max_s_0_CYSELG_2544,
      O => diff_min_max_s_0_CYMUXG_2554
    );
  diff_min_max_s_0_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X27Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => max_s_1_0,
      O => diff_min_max_s_0_CY0G_2552
    );
  diff_min_max_s_0_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X27Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_min_max_s_lut(1),
      O => diff_min_max_s_0_CYSELG_2544
    );
  Msub_diff_min_max_s_lut_1_Q : X_LUT4
    generic map(
      INIT => X"C3C3",
      LOC => "SLICE_X27Y22"
    )
    port map (
      ADR0 => VCC,
      ADR1 => max_s_1_0,
      ADR2 => min_s_1_0,
      ADR3 => VCC,
      O => Msub_diff_min_max_s_lut(1)
    );
  diff_min_max_s_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_min_max_s_2_XORF_2608,
      O => diff_min_max_s(2)
    );
  diff_min_max_s_2_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X27Y23"
    )
    port map (
      I0 => diff_min_max_s_2_CYINIT_2607,
      I1 => Msub_diff_min_max_s_lut(2),
      O => diff_min_max_s_2_XORF_2608
    );
  diff_min_max_s_2_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X27Y23"
    )
    port map (
      IA => diff_min_max_s_2_CY0F_2606,
      IB => diff_min_max_s_2_CYINIT_2607,
      SEL => diff_min_max_s_2_CYSELF_2594,
      O => Msub_diff_min_max_s_cy_2_Q
    );
  diff_min_max_s_2_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X27Y23"
    )
    port map (
      IA => diff_min_max_s_2_CY0F_2606,
      IB => diff_min_max_s_2_CY0F_2606,
      SEL => diff_min_max_s_2_CYSELF_2594,
      O => diff_min_max_s_2_CYMUXF2_2589
    );
  diff_min_max_s_2_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X27Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_min_max_s_cy_1_Q,
      O => diff_min_max_s_2_CYINIT_2607
    );
  diff_min_max_s_2_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X27Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => max_s_2_0,
      O => diff_min_max_s_2_CY0F_2606
    );
  diff_min_max_s_2_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X27Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_min_max_s_lut(2),
      O => diff_min_max_s_2_CYSELF_2594
    );
  diff_min_max_s_2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_min_max_s_2_XORG_2596,
      O => diff_min_max_s(3)
    );
  diff_min_max_s_2_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X27Y23"
    )
    port map (
      I0 => Msub_diff_min_max_s_cy_2_Q,
      I1 => Msub_diff_min_max_s_lut(3),
      O => diff_min_max_s_2_XORG_2596
    );
  diff_min_max_s_2_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_min_max_s_2_CYMUXFAST_2593,
      O => Msub_diff_min_max_s_cy_3_Q
    );
  diff_min_max_s_2_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X27Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_min_max_s_cy_1_Q,
      O => diff_min_max_s_2_FASTCARRY_2591
    );
  diff_min_max_s_2_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X27Y23"
    )
    port map (
      I0 => diff_min_max_s_2_CYSELG_2580,
      I1 => diff_min_max_s_2_CYSELF_2594,
      O => diff_min_max_s_2_CYAND_2592
    );
  diff_min_max_s_2_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X27Y23"
    )
    port map (
      IA => diff_min_max_s_2_CYMUXG2_2590,
      IB => diff_min_max_s_2_FASTCARRY_2591,
      SEL => diff_min_max_s_2_CYAND_2592,
      O => diff_min_max_s_2_CYMUXFAST_2593
    );
  diff_min_max_s_2_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X27Y23"
    )
    port map (
      IA => diff_min_max_s_2_CY0G_2588,
      IB => diff_min_max_s_2_CYMUXF2_2589,
      SEL => diff_min_max_s_2_CYSELG_2580,
      O => diff_min_max_s_2_CYMUXG2_2590
    );
  diff_min_max_s_2_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X27Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => max_s_3_0,
      O => diff_min_max_s_2_CY0G_2588
    );
  diff_min_max_s_2_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X27Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_min_max_s_lut(3),
      O => diff_min_max_s_2_CYSELG_2580
    );
  Msub_diff_min_max_s_lut_3_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X27Y23"
    )
    port map (
      ADR0 => min_s_3_0,
      ADR1 => max_s_3_0,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Msub_diff_min_max_s_lut(3)
    );
  diff_min_max_s_4_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_min_max_s_4_XORF_2647,
      O => diff_min_max_s(4)
    );
  diff_min_max_s_4_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X27Y24"
    )
    port map (
      I0 => diff_min_max_s_4_CYINIT_2646,
      I1 => Msub_diff_min_max_s_lut(4),
      O => diff_min_max_s_4_XORF_2647
    );
  diff_min_max_s_4_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X27Y24"
    )
    port map (
      IA => diff_min_max_s_4_CY0F_2645,
      IB => diff_min_max_s_4_CYINIT_2646,
      SEL => diff_min_max_s_4_CYSELF_2633,
      O => Msub_diff_min_max_s_cy_4_Q
    );
  diff_min_max_s_4_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X27Y24"
    )
    port map (
      IA => diff_min_max_s_4_CY0F_2645,
      IB => diff_min_max_s_4_CY0F_2645,
      SEL => diff_min_max_s_4_CYSELF_2633,
      O => diff_min_max_s_4_CYMUXF2_2628
    );
  diff_min_max_s_4_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X27Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_min_max_s_cy_3_Q,
      O => diff_min_max_s_4_CYINIT_2646
    );
  diff_min_max_s_4_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X27Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => max_s_4_0,
      O => diff_min_max_s_4_CY0F_2645
    );
  diff_min_max_s_4_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X27Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_min_max_s_lut(4),
      O => diff_min_max_s_4_CYSELF_2633
    );
  diff_min_max_s_4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_min_max_s_4_XORG_2635,
      O => diff_min_max_s(5)
    );
  diff_min_max_s_4_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X27Y24"
    )
    port map (
      I0 => Msub_diff_min_max_s_cy_4_Q,
      I1 => Msub_diff_min_max_s_lut(5),
      O => diff_min_max_s_4_XORG_2635
    );
  diff_min_max_s_4_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X27Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_min_max_s_cy_3_Q,
      O => diff_min_max_s_4_FASTCARRY_2630
    );
  diff_min_max_s_4_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X27Y24"
    )
    port map (
      I0 => diff_min_max_s_4_CYSELG_2619,
      I1 => diff_min_max_s_4_CYSELF_2633,
      O => diff_min_max_s_4_CYAND_2631
    );
  diff_min_max_s_4_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X27Y24"
    )
    port map (
      IA => diff_min_max_s_4_CYMUXG2_2629,
      IB => diff_min_max_s_4_FASTCARRY_2630,
      SEL => diff_min_max_s_4_CYAND_2631,
      O => diff_min_max_s_4_CYMUXFAST_2632
    );
  diff_min_max_s_4_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X27Y24"
    )
    port map (
      IA => diff_min_max_s_4_CY0G_2627,
      IB => diff_min_max_s_4_CYMUXF2_2628,
      SEL => diff_min_max_s_4_CYSELG_2619,
      O => diff_min_max_s_4_CYMUXG2_2629
    );
  diff_min_max_s_4_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X27Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => max_s_5_0,
      O => diff_min_max_s_4_CY0G_2627
    );
  diff_min_max_s_4_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X27Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_min_max_s_lut(5),
      O => diff_min_max_s_4_CYSELG_2619
    );
  Msub_diff_min_max_s_lut_5_Q : X_LUT4
    generic map(
      INIT => X"C3C3",
      LOC => "SLICE_X27Y24"
    )
    port map (
      ADR0 => VCC,
      ADR1 => max_s_5_0,
      ADR2 => min_s_5_0,
      ADR3 => VCC,
      O => Msub_diff_min_max_s_lut(5)
    );
  diff_min_max_s_6_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_min_max_s_6_XORF_2678,
      O => diff_min_max_s(6)
    );
  diff_min_max_s_6_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X27Y25"
    )
    port map (
      I0 => diff_min_max_s_6_CYINIT_2677,
      I1 => Msub_diff_min_max_s_lut(6),
      O => diff_min_max_s_6_XORF_2678
    );
  diff_min_max_s_6_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X27Y25"
    )
    port map (
      IA => diff_min_max_s_6_CY0F_2676,
      IB => diff_min_max_s_6_CYINIT_2677,
      SEL => diff_min_max_s_6_CYSELF_2668,
      O => Msub_diff_min_max_s_cy_6_Q
    );
  diff_min_max_s_6_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X27Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_min_max_s_4_CYMUXFAST_2632,
      O => diff_min_max_s_6_CYINIT_2677
    );
  diff_min_max_s_6_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X27Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => max_s_6_0,
      O => diff_min_max_s_6_CY0F_2676
    );
  diff_min_max_s_6_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X27Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_min_max_s_lut(6),
      O => diff_min_max_s_6_CYSELF_2668
    );
  diff_min_max_s_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_min_max_s_6_XORG_2665,
      O => diff_min_max_s(7)
    );
  diff_min_max_s_6_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X27Y25"
    )
    port map (
      I0 => Msub_diff_min_max_s_cy_6_Q,
      I1 => Msub_diff_min_max_s_lut(7),
      O => diff_min_max_s_6_XORG_2665
    );
  Mcompar_offset_s_cmp_ge0001_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X33Y22"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0001_cy_1_CY0F_2708,
      IB => Mcompar_offset_s_cmp_ge0001_cy_1_CYINIT_2709,
      SEL => Mcompar_offset_s_cmp_ge0001_cy_1_CYSELF_2700,
      O => Mcompar_offset_s_cmp_ge0001_cy(0)
    );
  Mcompar_offset_s_cmp_ge0001_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X33Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => Mcompar_offset_s_cmp_ge0001_cy_1_CYINIT_2709
    );
  Mcompar_offset_s_cmp_ge0001_cy_1_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X33Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_0_IBUF_1301,
      O => Mcompar_offset_s_cmp_ge0001_cy_1_CY0F_2708
    );
  Mcompar_offset_s_cmp_ge0001_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X33Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0001_lut(0),
      O => Mcompar_offset_s_cmp_ge0001_cy_1_CYSELF_2700
    );
  Mcompar_offset_s_cmp_ge0001_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X33Y22"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0001_cy_1_CY0G_2695,
      IB => Mcompar_offset_s_cmp_ge0001_cy(0),
      SEL => Mcompar_offset_s_cmp_ge0001_cy_1_CYSELG_2687,
      O => Mcompar_offset_s_cmp_ge0001_cy_1_CYMUXG_2697
    );
  Mcompar_offset_s_cmp_ge0001_cy_1_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X33Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_1_IBUF_1288,
      O => Mcompar_offset_s_cmp_ge0001_cy_1_CY0G_2695
    );
  Mcompar_offset_s_cmp_ge0001_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X33Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0001_lut(1),
      O => Mcompar_offset_s_cmp_ge0001_cy_1_CYSELG_2687
    );
  Mcompar_offset_s_cmp_ge0001_lut_1_Q : X_LUT4
    generic map(
      INIT => X"AA55",
      LOC => "SLICE_X33Y22"
    )
    port map (
      ADR0 => R_i_1_IBUF_1288,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => B_i_1_IBUF_1289,
      O => Mcompar_offset_s_cmp_ge0001_lut(1)
    );
  Mcompar_offset_s_cmp_ge0001_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y23"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0001_cy_3_CY0F_2740,
      IB => Mcompar_offset_s_cmp_ge0001_cy_3_CY0F_2740,
      SEL => Mcompar_offset_s_cmp_ge0001_cy_3_CYSELF_2731,
      O => Mcompar_offset_s_cmp_ge0001_cy_3_CYMUXF2_2726
    );
  Mcompar_offset_s_cmp_ge0001_cy_3_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X33Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_2_IBUF_1280,
      O => Mcompar_offset_s_cmp_ge0001_cy_3_CY0F_2740
    );
  Mcompar_offset_s_cmp_ge0001_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X33Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0001_lut(2),
      O => Mcompar_offset_s_cmp_ge0001_cy_3_CYSELF_2731
    );
  Mcompar_offset_s_cmp_ge0001_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X33Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0001_cy_1_CYMUXG_2697,
      O => Mcompar_offset_s_cmp_ge0001_cy_3_FASTCARRY_2728
    );
  Mcompar_offset_s_cmp_ge0001_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X33Y23"
    )
    port map (
      I0 => Mcompar_offset_s_cmp_ge0001_cy_3_CYSELG_2717,
      I1 => Mcompar_offset_s_cmp_ge0001_cy_3_CYSELF_2731,
      O => Mcompar_offset_s_cmp_ge0001_cy_3_CYAND_2729
    );
  Mcompar_offset_s_cmp_ge0001_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X33Y23"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0001_cy_3_CYMUXG2_2727,
      IB => Mcompar_offset_s_cmp_ge0001_cy_3_FASTCARRY_2728,
      SEL => Mcompar_offset_s_cmp_ge0001_cy_3_CYAND_2729,
      O => Mcompar_offset_s_cmp_ge0001_cy_3_CYMUXFAST_2730
    );
  Mcompar_offset_s_cmp_ge0001_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y23"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0001_cy_3_CY0G_2725,
      IB => Mcompar_offset_s_cmp_ge0001_cy_3_CYMUXF2_2726,
      SEL => Mcompar_offset_s_cmp_ge0001_cy_3_CYSELG_2717,
      O => Mcompar_offset_s_cmp_ge0001_cy_3_CYMUXG2_2727
    );
  Mcompar_offset_s_cmp_ge0001_cy_3_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X33Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_3_IBUF_1317,
      O => Mcompar_offset_s_cmp_ge0001_cy_3_CY0G_2725
    );
  Mcompar_offset_s_cmp_ge0001_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X33Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0001_lut(3),
      O => Mcompar_offset_s_cmp_ge0001_cy_3_CYSELG_2717
    );
  Mcompar_offset_s_cmp_ge0001_lut_3_Q : X_LUT4
    generic map(
      INIT => X"C3C3",
      LOC => "SLICE_X33Y23"
    )
    port map (
      ADR0 => VCC,
      ADR1 => R_i_3_IBUF_1317,
      ADR2 => B_i_3_IBUF_1318,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0001_lut(3)
    );
  Mcompar_offset_s_cmp_ge0001_cy_5_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y24"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0001_cy_5_CY0F_2771,
      IB => Mcompar_offset_s_cmp_ge0001_cy_5_CY0F_2771,
      SEL => Mcompar_offset_s_cmp_ge0001_cy_5_CYSELF_2762,
      O => Mcompar_offset_s_cmp_ge0001_cy_5_CYMUXF2_2757
    );
  Mcompar_offset_s_cmp_ge0001_cy_5_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X33Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_4_IBUF_1292,
      O => Mcompar_offset_s_cmp_ge0001_cy_5_CY0F_2771
    );
  Mcompar_offset_s_cmp_ge0001_cy_5_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X33Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0001_lut(4),
      O => Mcompar_offset_s_cmp_ge0001_cy_5_CYSELF_2762
    );
  Mcompar_offset_s_cmp_ge0001_cy_5_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X33Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0001_cy_3_CYMUXFAST_2730,
      O => Mcompar_offset_s_cmp_ge0001_cy_5_FASTCARRY_2759
    );
  Mcompar_offset_s_cmp_ge0001_cy_5_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X33Y24"
    )
    port map (
      I0 => Mcompar_offset_s_cmp_ge0001_cy_5_CYSELG_2748,
      I1 => Mcompar_offset_s_cmp_ge0001_cy_5_CYSELF_2762,
      O => Mcompar_offset_s_cmp_ge0001_cy_5_CYAND_2760
    );
  Mcompar_offset_s_cmp_ge0001_cy_5_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X33Y24"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0001_cy_5_CYMUXG2_2758,
      IB => Mcompar_offset_s_cmp_ge0001_cy_5_FASTCARRY_2759,
      SEL => Mcompar_offset_s_cmp_ge0001_cy_5_CYAND_2760,
      O => Mcompar_offset_s_cmp_ge0001_cy_5_CYMUXFAST_2761
    );
  Mcompar_offset_s_cmp_ge0001_cy_5_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y24"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0001_cy_5_CY0G_2756,
      IB => Mcompar_offset_s_cmp_ge0001_cy_5_CYMUXF2_2757,
      SEL => Mcompar_offset_s_cmp_ge0001_cy_5_CYSELG_2748,
      O => Mcompar_offset_s_cmp_ge0001_cy_5_CYMUXG2_2758
    );
  Mcompar_offset_s_cmp_ge0001_cy_5_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X33Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_5_IBUF_1313,
      O => Mcompar_offset_s_cmp_ge0001_cy_5_CY0G_2756
    );
  Mcompar_offset_s_cmp_ge0001_cy_5_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X33Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0001_lut(5),
      O => Mcompar_offset_s_cmp_ge0001_cy_5_CYSELG_2748
    );
  Mcompar_offset_s_cmp_ge0001_lut_5_Q : X_LUT4
    generic map(
      INIT => X"A5A5",
      LOC => "SLICE_X33Y24"
    )
    port map (
      ADR0 => R_i_5_IBUF_1313,
      ADR1 => VCC,
      ADR2 => B_i_5_IBUF_1314,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0001_lut(5)
    );
  offset_s_cmp_ge0001_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y25"
    )
    port map (
      IA => offset_s_cmp_ge0001_CY0F_2802,
      IB => offset_s_cmp_ge0001_CY0F_2802,
      SEL => offset_s_cmp_ge0001_CYSELF_2793,
      O => offset_s_cmp_ge0001_CYMUXF2_2788
    );
  offset_s_cmp_ge0001_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X33Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_6_IBUF_1305,
      O => offset_s_cmp_ge0001_CY0F_2802
    );
  offset_s_cmp_ge0001_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X33Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0001_lut(6),
      O => offset_s_cmp_ge0001_CYSELF_2793
    );
  offset_s_cmp_ge0001_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => offset_s_cmp_ge0001_CYMUXFAST_2792,
      O => offset_s_cmp_ge0001
    );
  offset_s_cmp_ge0001_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X33Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0001_cy_5_CYMUXFAST_2761,
      O => offset_s_cmp_ge0001_FASTCARRY_2790
    );
  offset_s_cmp_ge0001_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X33Y25"
    )
    port map (
      I0 => offset_s_cmp_ge0001_CYSELG_2779,
      I1 => offset_s_cmp_ge0001_CYSELF_2793,
      O => offset_s_cmp_ge0001_CYAND_2791
    );
  offset_s_cmp_ge0001_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X33Y25"
    )
    port map (
      IA => offset_s_cmp_ge0001_CYMUXG2_2789,
      IB => offset_s_cmp_ge0001_FASTCARRY_2790,
      SEL => offset_s_cmp_ge0001_CYAND_2791,
      O => offset_s_cmp_ge0001_CYMUXFAST_2792
    );
  offset_s_cmp_ge0001_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y25"
    )
    port map (
      IA => offset_s_cmp_ge0001_CY0G_2787,
      IB => offset_s_cmp_ge0001_CYMUXF2_2788,
      SEL => offset_s_cmp_ge0001_CYSELG_2779,
      O => offset_s_cmp_ge0001_CYMUXG2_2789
    );
  offset_s_cmp_ge0001_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X33Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_7_IBUF_1271,
      O => offset_s_cmp_ge0001_CY0G_2787
    );
  offset_s_cmp_ge0001_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X33Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0001_lut(7),
      O => offset_s_cmp_ge0001_CYSELG_2779
    );
  Mcompar_offset_s_cmp_ge0001_lut_7_Q : X_LUT4
    generic map(
      INIT => X"C3C3",
      LOC => "SLICE_X33Y25"
    )
    port map (
      ADR0 => VCC,
      ADR1 => R_i_7_IBUF_1271,
      ADR2 => B_i_7_IBUF_1273,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0001_lut(7)
    );
  Mcompar_min_s_cmp_le0003_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X36Y22"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0003_cy_1_CY0F_2831,
      IB => Mcompar_min_s_cmp_le0003_cy_1_CYINIT_2832,
      SEL => Mcompar_min_s_cmp_le0003_cy_1_CYSELF_2823,
      O => Mcompar_min_s_cmp_le0003_cy(0)
    );
  Mcompar_min_s_cmp_le0003_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X36Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => Mcompar_min_s_cmp_le0003_cy_1_CYINIT_2832
    );
  Mcompar_min_s_cmp_le0003_cy_1_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X36Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_0_IBUF_1326,
      O => Mcompar_min_s_cmp_le0003_cy_1_CY0F_2831
    );
  Mcompar_min_s_cmp_le0003_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X36Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0003_lut(0),
      O => Mcompar_min_s_cmp_le0003_cy_1_CYSELF_2823
    );
  Mcompar_min_s_cmp_le0003_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X36Y22"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0003_cy_1_CY0G_2818,
      IB => Mcompar_min_s_cmp_le0003_cy(0),
      SEL => Mcompar_min_s_cmp_le0003_cy_1_CYSELG_2810,
      O => Mcompar_min_s_cmp_le0003_cy_1_CYMUXG_2820
    );
  Mcompar_min_s_cmp_le0003_cy_1_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X36Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_1_IBUF_1289,
      O => Mcompar_min_s_cmp_le0003_cy_1_CY0G_2818
    );
  Mcompar_min_s_cmp_le0003_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X36Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0003_lut(1),
      O => Mcompar_min_s_cmp_le0003_cy_1_CYSELG_2810
    );
  Mcompar_min_s_cmp_le0003_lut_1_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X36Y22"
    )
    port map (
      ADR0 => B_i_1_IBUF_1289,
      ADR1 => G_i_1_IBUF_1287,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0003_lut(1)
    );
  Mcompar_min_s_cmp_le0003_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X36Y23"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0003_cy_3_CY0F_2863,
      IB => Mcompar_min_s_cmp_le0003_cy_3_CY0F_2863,
      SEL => Mcompar_min_s_cmp_le0003_cy_3_CYSELF_2854,
      O => Mcompar_min_s_cmp_le0003_cy_3_CYMUXF2_2849
    );
  Mcompar_min_s_cmp_le0003_cy_3_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X36Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_2_IBUF_1282,
      O => Mcompar_min_s_cmp_le0003_cy_3_CY0F_2863
    );
  Mcompar_min_s_cmp_le0003_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X36Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0003_lut(2),
      O => Mcompar_min_s_cmp_le0003_cy_3_CYSELF_2854
    );
  Mcompar_min_s_cmp_le0003_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X36Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0003_cy_1_CYMUXG_2820,
      O => Mcompar_min_s_cmp_le0003_cy_3_FASTCARRY_2851
    );
  Mcompar_min_s_cmp_le0003_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X36Y23"
    )
    port map (
      I0 => Mcompar_min_s_cmp_le0003_cy_3_CYSELG_2840,
      I1 => Mcompar_min_s_cmp_le0003_cy_3_CYSELF_2854,
      O => Mcompar_min_s_cmp_le0003_cy_3_CYAND_2852
    );
  Mcompar_min_s_cmp_le0003_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X36Y23"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0003_cy_3_CYMUXG2_2850,
      IB => Mcompar_min_s_cmp_le0003_cy_3_FASTCARRY_2851,
      SEL => Mcompar_min_s_cmp_le0003_cy_3_CYAND_2852,
      O => Mcompar_min_s_cmp_le0003_cy_3_CYMUXFAST_2853
    );
  Mcompar_min_s_cmp_le0003_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X36Y23"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0003_cy_3_CY0G_2848,
      IB => Mcompar_min_s_cmp_le0003_cy_3_CYMUXF2_2849,
      SEL => Mcompar_min_s_cmp_le0003_cy_3_CYSELG_2840,
      O => Mcompar_min_s_cmp_le0003_cy_3_CYMUXG2_2850
    );
  Mcompar_min_s_cmp_le0003_cy_3_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X36Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_3_IBUF_1318,
      O => Mcompar_min_s_cmp_le0003_cy_3_CY0G_2848
    );
  Mcompar_min_s_cmp_le0003_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X36Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0003_lut(3),
      O => Mcompar_min_s_cmp_le0003_cy_3_CYSELG_2840
    );
  Mcompar_min_s_cmp_le0003_lut_3_Q : X_LUT4
    generic map(
      INIT => X"A5A5",
      LOC => "SLICE_X36Y23"
    )
    port map (
      ADR0 => B_i_3_IBUF_1318,
      ADR1 => VCC,
      ADR2 => G_i_3_IBUF_1319,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0003_lut(3)
    );
  Mcompar_min_s_cmp_le0003_cy_5_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X36Y24"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0003_cy_5_CY0F_2894,
      IB => Mcompar_min_s_cmp_le0003_cy_5_CY0F_2894,
      SEL => Mcompar_min_s_cmp_le0003_cy_5_CYSELF_2885,
      O => Mcompar_min_s_cmp_le0003_cy_5_CYMUXF2_2880
    );
  Mcompar_min_s_cmp_le0003_cy_5_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X36Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_4_IBUF_1293,
      O => Mcompar_min_s_cmp_le0003_cy_5_CY0F_2894
    );
  Mcompar_min_s_cmp_le0003_cy_5_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X36Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0003_lut(4),
      O => Mcompar_min_s_cmp_le0003_cy_5_CYSELF_2885
    );
  Mcompar_min_s_cmp_le0003_cy_5_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X36Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0003_cy_3_CYMUXFAST_2853,
      O => Mcompar_min_s_cmp_le0003_cy_5_FASTCARRY_2882
    );
  Mcompar_min_s_cmp_le0003_cy_5_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X36Y24"
    )
    port map (
      I0 => Mcompar_min_s_cmp_le0003_cy_5_CYSELG_2871,
      I1 => Mcompar_min_s_cmp_le0003_cy_5_CYSELF_2885,
      O => Mcompar_min_s_cmp_le0003_cy_5_CYAND_2883
    );
  Mcompar_min_s_cmp_le0003_cy_5_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X36Y24"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0003_cy_5_CYMUXG2_2881,
      IB => Mcompar_min_s_cmp_le0003_cy_5_FASTCARRY_2882,
      SEL => Mcompar_min_s_cmp_le0003_cy_5_CYAND_2883,
      O => Mcompar_min_s_cmp_le0003_cy_5_CYMUXFAST_2884
    );
  Mcompar_min_s_cmp_le0003_cy_5_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X36Y24"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0003_cy_5_CY0G_2879,
      IB => Mcompar_min_s_cmp_le0003_cy_5_CYMUXF2_2880,
      SEL => Mcompar_min_s_cmp_le0003_cy_5_CYSELG_2871,
      O => Mcompar_min_s_cmp_le0003_cy_5_CYMUXG2_2881
    );
  Mcompar_min_s_cmp_le0003_cy_5_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X36Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_5_IBUF_1314,
      O => Mcompar_min_s_cmp_le0003_cy_5_CY0G_2879
    );
  Mcompar_min_s_cmp_le0003_cy_5_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X36Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0003_lut(5),
      O => Mcompar_min_s_cmp_le0003_cy_5_CYSELG_2871
    );
  Mcompar_min_s_cmp_le0003_lut_5_Q : X_LUT4
    generic map(
      INIT => X"C3C3",
      LOC => "SLICE_X36Y24"
    )
    port map (
      ADR0 => VCC,
      ADR1 => B_i_5_IBUF_1314,
      ADR2 => G_i_5_IBUF_1312,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0003_lut(5)
    );
  min_s_cmp_le0003_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X36Y25"
    )
    port map (
      IA => min_s_cmp_le0003_CY0F_2925,
      IB => min_s_cmp_le0003_CY0F_2925,
      SEL => min_s_cmp_le0003_CYSELF_2916,
      O => min_s_cmp_le0003_CYMUXF2_2911
    );
  min_s_cmp_le0003_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X36Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_6_IBUF_1306,
      O => min_s_cmp_le0003_CY0F_2925
    );
  min_s_cmp_le0003_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X36Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0003_lut(6),
      O => min_s_cmp_le0003_CYSELF_2916
    );
  min_s_cmp_le0003_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X36Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => min_s_cmp_le0003_CYMUXFAST_2915,
      O => min_s_cmp_le0003
    );
  min_s_cmp_le0003_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X36Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0003_cy_5_CYMUXFAST_2884,
      O => min_s_cmp_le0003_FASTCARRY_2913
    );
  min_s_cmp_le0003_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X36Y25"
    )
    port map (
      I0 => min_s_cmp_le0003_CYSELG_2902,
      I1 => min_s_cmp_le0003_CYSELF_2916,
      O => min_s_cmp_le0003_CYAND_2914
    );
  min_s_cmp_le0003_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X36Y25"
    )
    port map (
      IA => min_s_cmp_le0003_CYMUXG2_2912,
      IB => min_s_cmp_le0003_FASTCARRY_2913,
      SEL => min_s_cmp_le0003_CYAND_2914,
      O => min_s_cmp_le0003_CYMUXFAST_2915
    );
  min_s_cmp_le0003_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X36Y25"
    )
    port map (
      IA => min_s_cmp_le0003_CY0G_2910,
      IB => min_s_cmp_le0003_CYMUXF2_2911,
      SEL => min_s_cmp_le0003_CYSELG_2902,
      O => min_s_cmp_le0003_CYMUXG2_2912
    );
  min_s_cmp_le0003_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X36Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_7_IBUF_1273,
      O => min_s_cmp_le0003_CY0G_2910
    );
  min_s_cmp_le0003_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X36Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0003_lut(7),
      O => min_s_cmp_le0003_CYSELG_2902
    );
  Mcompar_min_s_cmp_le0003_lut_7_Q : X_LUT4
    generic map(
      INIT => X"A5A5",
      LOC => "SLICE_X36Y25"
    )
    port map (
      ADR0 => B_i_7_IBUF_1273,
      ADR1 => VCC,
      ADR2 => G_i_7_IBUF_1275,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0003_lut(7)
    );
  diff_nominat_s_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_0_XORF_2960,
      O => diff_nominat_s(0)
    );
  diff_nominat_s_0_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X22Y20"
    )
    port map (
      I0 => diff_nominat_s_0_CYINIT_2959,
      I1 => Msub_diff_nominat_s_lut(0),
      O => diff_nominat_s_0_XORF_2960
    );
  diff_nominat_s_0_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X22Y20"
    )
    port map (
      IA => diff_nominat_s_0_CY0F_2958,
      IB => diff_nominat_s_0_CYINIT_2959,
      SEL => diff_nominat_s_0_CYSELF_2952,
      O => Msub_diff_nominat_s_cy(0)
    );
  diff_nominat_s_0_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X22Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => diff_nominat_s_0_CYINIT_2959
    );
  diff_nominat_s_0_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X22Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_mux0000_0_0,
      O => diff_nominat_s_0_CY0F_2958
    );
  diff_nominat_s_0_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X22Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_nominat_s_lut(0),
      O => diff_nominat_s_0_CYSELF_2952
    );
  diff_nominat_s_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_0_XORG_2948,
      O => diff_nominat_s(1)
    );
  diff_nominat_s_0_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X22Y20"
    )
    port map (
      I0 => Msub_diff_nominat_s_cy(0),
      I1 => Msub_diff_nominat_s_lut(1),
      O => diff_nominat_s_0_XORG_2948
    );
  diff_nominat_s_0_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_0_CYMUXG_2947,
      O => Msub_diff_nominat_s_cy(1)
    );
  diff_nominat_s_0_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X22Y20"
    )
    port map (
      IA => diff_nominat_s_0_CY0G_2945,
      IB => Msub_diff_nominat_s_cy(0),
      SEL => diff_nominat_s_0_CYSELG_2939,
      O => diff_nominat_s_0_CYMUXG_2947
    );
  diff_nominat_s_0_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X22Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_mux0000_1_0,
      O => diff_nominat_s_0_CY0G_2945
    );
  diff_nominat_s_0_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X22Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_nominat_s_lut(1),
      O => diff_nominat_s_0_CYSELG_2939
    );
  Msub_diff_nominat_s_lut_1_Q : X_LUT4
    generic map(
      INIT => X"A965",
      LOC => "SLICE_X22Y20"
    )
    port map (
      ADR0 => diff_nominat_s_mux0000_1_0,
      ADR1 => offset_s_0_0,
      ADR2 => B_i_1_IBUF_1289,
      ADR3 => N35_0,
      O => Msub_diff_nominat_s_lut(1)
    );
  diff_nominat_s_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_2_XORF_2999,
      O => diff_nominat_s(2)
    );
  diff_nominat_s_2_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X22Y21"
    )
    port map (
      I0 => diff_nominat_s_2_CYINIT_2998,
      I1 => Msub_diff_nominat_s_lut(2),
      O => diff_nominat_s_2_XORF_2999
    );
  diff_nominat_s_2_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X22Y21"
    )
    port map (
      IA => diff_nominat_s_2_CY0F_2997,
      IB => diff_nominat_s_2_CYINIT_2998,
      SEL => diff_nominat_s_2_CYSELF_2987,
      O => Msub_diff_nominat_s_cy(2)
    );
  diff_nominat_s_2_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X22Y21"
    )
    port map (
      IA => diff_nominat_s_2_CY0F_2997,
      IB => diff_nominat_s_2_CY0F_2997,
      SEL => diff_nominat_s_2_CYSELF_2987,
      O => diff_nominat_s_2_CYMUXF2_2982
    );
  diff_nominat_s_2_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X22Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_nominat_s_cy(1),
      O => diff_nominat_s_2_CYINIT_2998
    );
  diff_nominat_s_2_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X22Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_mux0000_2_0,
      O => diff_nominat_s_2_CY0F_2997
    );
  diff_nominat_s_2_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X22Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_nominat_s_lut(2),
      O => diff_nominat_s_2_CYSELF_2987
    );
  diff_nominat_s_2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_2_XORG_2989,
      O => diff_nominat_s(3)
    );
  diff_nominat_s_2_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X22Y21"
    )
    port map (
      I0 => Msub_diff_nominat_s_cy(2),
      I1 => Msub_diff_nominat_s_lut(3),
      O => diff_nominat_s_2_XORG_2989
    );
  diff_nominat_s_2_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_2_CYMUXFAST_2986,
      O => Msub_diff_nominat_s_cy(3)
    );
  diff_nominat_s_2_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X22Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_nominat_s_cy(1),
      O => diff_nominat_s_2_FASTCARRY_2984
    );
  diff_nominat_s_2_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X22Y21"
    )
    port map (
      I0 => diff_nominat_s_2_CYSELG_2975,
      I1 => diff_nominat_s_2_CYSELF_2987,
      O => diff_nominat_s_2_CYAND_2985
    );
  diff_nominat_s_2_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X22Y21"
    )
    port map (
      IA => diff_nominat_s_2_CYMUXG2_2983,
      IB => diff_nominat_s_2_FASTCARRY_2984,
      SEL => diff_nominat_s_2_CYAND_2985,
      O => diff_nominat_s_2_CYMUXFAST_2986
    );
  diff_nominat_s_2_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X22Y21"
    )
    port map (
      IA => diff_nominat_s_2_CY0G_2981,
      IB => diff_nominat_s_2_CYMUXF2_2982,
      SEL => diff_nominat_s_2_CYSELG_2975,
      O => diff_nominat_s_2_CYMUXG2_2983
    );
  diff_nominat_s_2_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X22Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_mux0000_3_0,
      O => diff_nominat_s_2_CY0G_2981
    );
  diff_nominat_s_2_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X22Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_nominat_s_lut(3),
      O => diff_nominat_s_2_CYSELG_2975
    );
  Msub_diff_nominat_s_lut_3_Q : X_LUT4
    generic map(
      INIT => X"A695",
      LOC => "SLICE_X22Y21"
    )
    port map (
      ADR0 => diff_nominat_s_mux0000_3_0,
      ADR1 => offset_s_0_0,
      ADR2 => N31_0,
      ADR3 => B_i_3_IBUF_1318,
      O => Msub_diff_nominat_s_lut(3)
    );
  diff_nominat_s_4_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_4_XORF_3038,
      O => diff_nominat_s(4)
    );
  diff_nominat_s_4_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X22Y22"
    )
    port map (
      I0 => diff_nominat_s_4_CYINIT_3037,
      I1 => Msub_diff_nominat_s_lut(4),
      O => diff_nominat_s_4_XORF_3038
    );
  diff_nominat_s_4_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X22Y22"
    )
    port map (
      IA => diff_nominat_s_4_CY0F_3036,
      IB => diff_nominat_s_4_CYINIT_3037,
      SEL => diff_nominat_s_4_CYSELF_3026,
      O => Msub_diff_nominat_s_cy(4)
    );
  diff_nominat_s_4_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X22Y22"
    )
    port map (
      IA => diff_nominat_s_4_CY0F_3036,
      IB => diff_nominat_s_4_CY0F_3036,
      SEL => diff_nominat_s_4_CYSELF_3026,
      O => diff_nominat_s_4_CYMUXF2_3021
    );
  diff_nominat_s_4_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X22Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_nominat_s_cy(3),
      O => diff_nominat_s_4_CYINIT_3037
    );
  diff_nominat_s_4_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X22Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_mux0000_4_0,
      O => diff_nominat_s_4_CY0F_3036
    );
  diff_nominat_s_4_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X22Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_nominat_s_lut(4),
      O => diff_nominat_s_4_CYSELF_3026
    );
  diff_nominat_s_4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_4_XORG_3028,
      O => diff_nominat_s(5)
    );
  diff_nominat_s_4_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X22Y22"
    )
    port map (
      I0 => Msub_diff_nominat_s_cy(4),
      I1 => Msub_diff_nominat_s_lut(5),
      O => diff_nominat_s_4_XORG_3028
    );
  diff_nominat_s_4_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_4_CYMUXFAST_3025,
      O => Msub_diff_nominat_s_cy(5)
    );
  diff_nominat_s_4_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X22Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_nominat_s_cy(3),
      O => diff_nominat_s_4_FASTCARRY_3023
    );
  diff_nominat_s_4_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X22Y22"
    )
    port map (
      I0 => diff_nominat_s_4_CYSELG_3014,
      I1 => diff_nominat_s_4_CYSELF_3026,
      O => diff_nominat_s_4_CYAND_3024
    );
  diff_nominat_s_4_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X22Y22"
    )
    port map (
      IA => diff_nominat_s_4_CYMUXG2_3022,
      IB => diff_nominat_s_4_FASTCARRY_3023,
      SEL => diff_nominat_s_4_CYAND_3024,
      O => diff_nominat_s_4_CYMUXFAST_3025
    );
  diff_nominat_s_4_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X22Y22"
    )
    port map (
      IA => diff_nominat_s_4_CY0G_3020,
      IB => diff_nominat_s_4_CYMUXF2_3021,
      SEL => diff_nominat_s_4_CYSELG_3014,
      O => diff_nominat_s_4_CYMUXG2_3022
    );
  diff_nominat_s_4_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X22Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_mux0000_5_0,
      O => diff_nominat_s_4_CY0G_3020
    );
  diff_nominat_s_4_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X22Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_nominat_s_lut(5),
      O => diff_nominat_s_4_CYSELG_3014
    );
  Msub_diff_nominat_s_lut_5_Q : X_LUT4
    generic map(
      INIT => X"A965",
      LOC => "SLICE_X22Y22"
    )
    port map (
      ADR0 => diff_nominat_s_mux0000_5_0,
      ADR1 => offset_s_0_0,
      ADR2 => B_i_5_IBUF_1314,
      ADR3 => N27_0,
      O => Msub_diff_nominat_s_lut(5)
    );
  diff_nominat_s_6_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_6_XORF_3077,
      O => diff_nominat_s(6)
    );
  diff_nominat_s_6_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X22Y23"
    )
    port map (
      I0 => diff_nominat_s_6_CYINIT_3076,
      I1 => Msub_diff_nominat_s_lut(6),
      O => diff_nominat_s_6_XORF_3077
    );
  diff_nominat_s_6_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X22Y23"
    )
    port map (
      IA => diff_nominat_s_6_CY0F_3075,
      IB => diff_nominat_s_6_CYINIT_3076,
      SEL => diff_nominat_s_6_CYSELF_3065,
      O => Msub_diff_nominat_s_cy(6)
    );
  diff_nominat_s_6_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X22Y23"
    )
    port map (
      IA => diff_nominat_s_6_CY0F_3075,
      IB => diff_nominat_s_6_CY0F_3075,
      SEL => diff_nominat_s_6_CYSELF_3065,
      O => diff_nominat_s_6_CYMUXF2_3060
    );
  diff_nominat_s_6_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X22Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_nominat_s_cy(5),
      O => diff_nominat_s_6_CYINIT_3076
    );
  diff_nominat_s_6_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X22Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_mux0000_6_0,
      O => diff_nominat_s_6_CY0F_3075
    );
  diff_nominat_s_6_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X22Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_nominat_s_lut(6),
      O => diff_nominat_s_6_CYSELF_3065
    );
  diff_nominat_s_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_6_XORG_3067,
      O => diff_nominat_s(7)
    );
  diff_nominat_s_6_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X22Y23"
    )
    port map (
      I0 => Msub_diff_nominat_s_cy(6),
      I1 => Msub_diff_nominat_s_lut(7),
      O => diff_nominat_s_6_XORG_3067
    );
  diff_nominat_s_6_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X22Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_nominat_s_cy(5),
      O => diff_nominat_s_6_FASTCARRY_3062
    );
  diff_nominat_s_6_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X22Y23"
    )
    port map (
      I0 => diff_nominat_s_6_CYSELG_3053,
      I1 => diff_nominat_s_6_CYSELF_3065,
      O => diff_nominat_s_6_CYAND_3063
    );
  diff_nominat_s_6_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X22Y23"
    )
    port map (
      IA => diff_nominat_s_6_CYMUXG2_3061,
      IB => diff_nominat_s_6_FASTCARRY_3062,
      SEL => diff_nominat_s_6_CYAND_3063,
      O => diff_nominat_s_6_CYMUXFAST_3064
    );
  diff_nominat_s_6_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X22Y23"
    )
    port map (
      IA => diff_nominat_s_6_CY0G_3059,
      IB => diff_nominat_s_6_CYMUXF2_3060,
      SEL => diff_nominat_s_6_CYSELG_3053,
      O => diff_nominat_s_6_CYMUXG2_3061
    );
  diff_nominat_s_6_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X22Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_mux0000_7_0,
      O => diff_nominat_s_6_CY0G_3059
    );
  diff_nominat_s_6_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X22Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Msub_diff_nominat_s_lut(7),
      O => diff_nominat_s_6_CYSELG_3053
    );
  Msub_diff_nominat_s_lut_7_Q : X_LUT4
    generic map(
      INIT => X"A695",
      LOC => "SLICE_X22Y23"
    )
    port map (
      ADR0 => diff_nominat_s_mux0000_7_0,
      ADR1 => offset_s_0_0,
      ADR2 => N23_0,
      ADR3 => B_i_7_IBUF_1273,
      O => Msub_diff_nominat_s_lut(7)
    );
  H_bias_s_0_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X6Y22"
    )
    port map (
      IA => H_bias_s_0_CY0F_3126,
      IB => H_bias_s_0_CYINIT_3127,
      SEL => H_bias_s_0_CYSELF_3119,
      O => Madd_H_bias_s_Madd_cy_0_Q
    );
  H_bias_s_0_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X6Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => H_bias_s_0_CYINIT_3127
    );
  H_bias_s_0_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X6Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_large_s(9),
      O => H_bias_s_0_CY0F_3126
    );
  H_bias_s_0_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X6Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_bias_s(0),
      O => H_bias_s_0_CYSELF_3119
    );
  H_bias_s_0_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X6Y22"
    )
    port map (
      I0 => Madd_H_bias_s_Madd_cy_0_Q,
      I1 => Madd_H_bias_s_Madd_lut(1),
      O => H_bias_s_0_XORG_3115
    );
  H_bias_s_0_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X6Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_bias_s_0_CYMUXG_3114,
      O => Madd_H_bias_s_Madd_cy_1_Q
    );
  H_bias_s_0_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X6Y22"
    )
    port map (
      IA => H_bias_s_0_CY0G_3112,
      IB => Madd_H_bias_s_Madd_cy_0_Q,
      SEL => H_bias_s_0_CYSELG_3106,
      O => H_bias_s_0_CYMUXG_3114
    );
  H_bias_s_0_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X6Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_large_s(10),
      O => H_bias_s_0_CY0G_3112
    );
  H_bias_s_0_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X6Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_H_bias_s_Madd_lut(1),
      O => H_bias_s_0_CYSELG_3106
    );
  Madd_H_bias_s_Madd_lut_1_Q : X_LUT4
    generic map(
      INIT => X"9C3C",
      LOC => "SLICE_X6Y22"
    )
    port map (
      ADR0 => offset_s_cmp_ge0003,
      ADR1 => H_large_s(10),
      ADR2 => offset_s_0_0,
      ADR3 => offset_s_cmp_ge0002,
      O => Madd_H_bias_s_Madd_lut(1)
    );
  H_bias_s_2_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X6Y23"
    )
    port map (
      I0 => H_bias_s_2_CYINIT_3165,
      I1 => Madd_H_bias_s_Madd_lut(2),
      O => H_bias_s_2_XORF_3166
    );
  H_bias_s_2_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X6Y23"
    )
    port map (
      IA => H_bias_s_2_CY0F_3164,
      IB => H_bias_s_2_CYINIT_3165,
      SEL => H_bias_s_2_CYSELF_3154,
      O => Madd_H_bias_s_Madd_cy_2_Q
    );
  H_bias_s_2_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X6Y23"
    )
    port map (
      IA => H_bias_s_2_CY0F_3164,
      IB => H_bias_s_2_CY0F_3164,
      SEL => H_bias_s_2_CYSELF_3154,
      O => H_bias_s_2_CYMUXF2_3149
    );
  H_bias_s_2_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X6Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_H_bias_s_Madd_cy_1_Q,
      O => H_bias_s_2_CYINIT_3165
    );
  H_bias_s_2_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X6Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_large_s(11),
      O => H_bias_s_2_CY0F_3164
    );
  H_bias_s_2_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X6Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_H_bias_s_Madd_lut(2),
      O => H_bias_s_2_CYSELF_3154
    );
  H_bias_s_2_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X6Y23"
    )
    port map (
      I0 => Madd_H_bias_s_Madd_cy_2_Q,
      I1 => Madd_H_bias_s_Madd_lut(3),
      O => H_bias_s_2_XORG_3156
    );
  H_bias_s_2_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X6Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_bias_s_2_CYMUXFAST_3153,
      O => Madd_H_bias_s_Madd_cy_3_Q
    );
  H_bias_s_2_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X6Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_H_bias_s_Madd_cy_1_Q,
      O => H_bias_s_2_FASTCARRY_3151
    );
  H_bias_s_2_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X6Y23"
    )
    port map (
      I0 => H_bias_s_2_CYSELG_3142,
      I1 => H_bias_s_2_CYSELF_3154,
      O => H_bias_s_2_CYAND_3152
    );
  H_bias_s_2_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X6Y23"
    )
    port map (
      IA => H_bias_s_2_CYMUXG2_3150,
      IB => H_bias_s_2_FASTCARRY_3151,
      SEL => H_bias_s_2_CYAND_3152,
      O => H_bias_s_2_CYMUXFAST_3153
    );
  H_bias_s_2_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X6Y23"
    )
    port map (
      IA => H_bias_s_2_CY0G_3148,
      IB => H_bias_s_2_CYMUXF2_3149,
      SEL => H_bias_s_2_CYSELG_3142,
      O => H_bias_s_2_CYMUXG2_3150
    );
  H_bias_s_2_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X6Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_large_s(12),
      O => H_bias_s_2_CY0G_3148
    );
  H_bias_s_2_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X6Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_H_bias_s_Madd_lut(3),
      O => H_bias_s_2_CYSELG_3142
    );
  Madd_H_bias_s_Madd_lut_3_Q : X_LUT4
    generic map(
      INIT => X"9C3C",
      LOC => "SLICE_X6Y23"
    )
    port map (
      ADR0 => offset_s_cmp_ge0003,
      ADR1 => H_large_s(12),
      ADR2 => offset_s_0_0,
      ADR3 => offset_s_cmp_ge0002,
      O => Madd_H_bias_s_Madd_lut(3)
    );
  H_bias_s_4_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X6Y24"
    )
    port map (
      I0 => H_bias_s_4_CYINIT_3204,
      I1 => Madd_H_bias_s_Madd_lut(4),
      O => H_bias_s_4_XORF_3205
    );
  H_bias_s_4_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X6Y24"
    )
    port map (
      IA => H_bias_s_4_CY0F_3203,
      IB => H_bias_s_4_CYINIT_3204,
      SEL => H_bias_s_4_CYSELF_3193,
      O => Madd_H_bias_s_Madd_cy_4_Q
    );
  H_bias_s_4_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X6Y24"
    )
    port map (
      IA => H_bias_s_4_CY0F_3203,
      IB => H_bias_s_4_CY0F_3203,
      SEL => H_bias_s_4_CYSELF_3193,
      O => H_bias_s_4_CYMUXF2_3188
    );
  H_bias_s_4_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X6Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_H_bias_s_Madd_cy_3_Q,
      O => H_bias_s_4_CYINIT_3204
    );
  H_bias_s_4_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X6Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_large_s(13),
      O => H_bias_s_4_CY0F_3203
    );
  H_bias_s_4_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X6Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_H_bias_s_Madd_lut(4),
      O => H_bias_s_4_CYSELF_3193
    );
  H_bias_s_4_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X6Y24"
    )
    port map (
      I0 => Madd_H_bias_s_Madd_cy_4_Q,
      I1 => Madd_H_bias_s_Madd_lut(5),
      O => H_bias_s_4_XORG_3195
    );
  H_bias_s_4_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X6Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_H_bias_s_Madd_cy_3_Q,
      O => H_bias_s_4_FASTCARRY_3190
    );
  H_bias_s_4_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X6Y24"
    )
    port map (
      I0 => H_bias_s_4_CYSELG_3181,
      I1 => H_bias_s_4_CYSELF_3193,
      O => H_bias_s_4_CYAND_3191
    );
  H_bias_s_4_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X6Y24"
    )
    port map (
      IA => H_bias_s_4_CYMUXG2_3189,
      IB => H_bias_s_4_FASTCARRY_3190,
      SEL => H_bias_s_4_CYAND_3191,
      O => H_bias_s_4_CYMUXFAST_3192
    );
  H_bias_s_4_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X6Y24"
    )
    port map (
      IA => H_bias_s_4_CY0G_3187,
      IB => H_bias_s_4_CYMUXF2_3188,
      SEL => H_bias_s_4_CYSELG_3181,
      O => H_bias_s_4_CYMUXG2_3189
    );
  H_bias_s_4_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X6Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_large_s(14),
      O => H_bias_s_4_CY0G_3187
    );
  H_bias_s_4_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X6Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_H_bias_s_Madd_lut(5),
      O => H_bias_s_4_CYSELG_3181
    );
  Madd_H_bias_s_Madd_lut_5_Q : X_LUT4
    generic map(
      INIT => X"9A5A",
      LOC => "SLICE_X6Y24"
    )
    port map (
      ADR0 => H_large_s(14),
      ADR1 => offset_s_cmp_ge0003,
      ADR2 => offset_s_0_0,
      ADR3 => offset_s_cmp_ge0002,
      O => Madd_H_bias_s_Madd_lut(5)
    );
  H_bias_s_6_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X6Y25"
    )
    port map (
      I0 => H_bias_s_6_CYINIT_3235,
      I1 => Madd_H_bias_s_Madd_lut(6),
      O => H_bias_s_6_XORF_3236
    );
  H_bias_s_6_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X6Y25"
    )
    port map (
      IA => H_bias_s_6_CY0F_3234,
      IB => H_bias_s_6_CYINIT_3235,
      SEL => H_bias_s_6_CYSELF_3228,
      O => Madd_H_bias_s_Madd_cy_6_Q
    );
  H_bias_s_6_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X6Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_bias_s_4_CYMUXFAST_3192,
      O => H_bias_s_6_CYINIT_3235
    );
  H_bias_s_6_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X6Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_large_s(15),
      O => H_bias_s_6_CY0F_3234
    );
  H_bias_s_6_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X6Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_H_bias_s_Madd_lut(6),
      O => H_bias_s_6_CYSELF_3228
    );
  H_bias_s_6_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X6Y25"
    )
    port map (
      I0 => Madd_H_bias_s_Madd_cy_6_Q,
      I1 => Madd_H_bias_s_Madd_lut(7),
      O => H_bias_s_6_XORG_3225
    );
  Mcompar_min_s_cmp_le0000_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X38Y24"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0000_cy_1_CY0F_3266,
      IB => Mcompar_min_s_cmp_le0000_cy_1_CYINIT_3267,
      SEL => Mcompar_min_s_cmp_le0000_cy_1_CYSELF_3258,
      O => Mcompar_min_s_cmp_le0000_cy(0)
    );
  Mcompar_min_s_cmp_le0000_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X38Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => Mcompar_min_s_cmp_le0000_cy_1_CYINIT_3267
    );
  Mcompar_min_s_cmp_le0000_cy_1_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X38Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_0_IBUF_1300,
      O => Mcompar_min_s_cmp_le0000_cy_1_CY0F_3266
    );
  Mcompar_min_s_cmp_le0000_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X38Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0000_lut(0),
      O => Mcompar_min_s_cmp_le0000_cy_1_CYSELF_3258
    );
  Mcompar_min_s_cmp_le0000_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X38Y24"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0000_cy_1_CY0G_3253,
      IB => Mcompar_min_s_cmp_le0000_cy(0),
      SEL => Mcompar_min_s_cmp_le0000_cy_1_CYSELG_3245,
      O => Mcompar_min_s_cmp_le0000_cy_1_CYMUXG_3255
    );
  Mcompar_min_s_cmp_le0000_cy_1_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X38Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_1_IBUF_1287,
      O => Mcompar_min_s_cmp_le0000_cy_1_CY0G_3253
    );
  Mcompar_min_s_cmp_le0000_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X38Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0000_lut(1),
      O => Mcompar_min_s_cmp_le0000_cy_1_CYSELG_3245
    );
  Mcompar_min_s_cmp_le0000_lut_1_Q : X_LUT4
    generic map(
      INIT => X"CC33",
      LOC => "SLICE_X38Y24"
    )
    port map (
      ADR0 => VCC,
      ADR1 => G_i_1_IBUF_1287,
      ADR2 => VCC,
      ADR3 => R_i_1_IBUF_1288,
      O => Mcompar_min_s_cmp_le0000_lut(1)
    );
  Mcompar_min_s_cmp_le0000_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X38Y25"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0000_cy_3_CY0F_3298,
      IB => Mcompar_min_s_cmp_le0000_cy_3_CY0F_3298,
      SEL => Mcompar_min_s_cmp_le0000_cy_3_CYSELF_3289,
      O => Mcompar_min_s_cmp_le0000_cy_3_CYMUXF2_3284
    );
  Mcompar_min_s_cmp_le0000_cy_3_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X38Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_2_IBUF_1284,
      O => Mcompar_min_s_cmp_le0000_cy_3_CY0F_3298
    );
  Mcompar_min_s_cmp_le0000_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X38Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0000_lut(2),
      O => Mcompar_min_s_cmp_le0000_cy_3_CYSELF_3289
    );
  Mcompar_min_s_cmp_le0000_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X38Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0000_cy_1_CYMUXG_3255,
      O => Mcompar_min_s_cmp_le0000_cy_3_FASTCARRY_3286
    );
  Mcompar_min_s_cmp_le0000_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X38Y25"
    )
    port map (
      I0 => Mcompar_min_s_cmp_le0000_cy_3_CYSELG_3275,
      I1 => Mcompar_min_s_cmp_le0000_cy_3_CYSELF_3289,
      O => Mcompar_min_s_cmp_le0000_cy_3_CYAND_3287
    );
  Mcompar_min_s_cmp_le0000_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X38Y25"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0000_cy_3_CYMUXG2_3285,
      IB => Mcompar_min_s_cmp_le0000_cy_3_FASTCARRY_3286,
      SEL => Mcompar_min_s_cmp_le0000_cy_3_CYAND_3287,
      O => Mcompar_min_s_cmp_le0000_cy_3_CYMUXFAST_3288
    );
  Mcompar_min_s_cmp_le0000_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X38Y25"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0000_cy_3_CY0G_3283,
      IB => Mcompar_min_s_cmp_le0000_cy_3_CYMUXF2_3284,
      SEL => Mcompar_min_s_cmp_le0000_cy_3_CYSELG_3275,
      O => Mcompar_min_s_cmp_le0000_cy_3_CYMUXG2_3285
    );
  Mcompar_min_s_cmp_le0000_cy_3_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X38Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_3_IBUF_1319,
      O => Mcompar_min_s_cmp_le0000_cy_3_CY0G_3283
    );
  Mcompar_min_s_cmp_le0000_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X38Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0000_lut(3),
      O => Mcompar_min_s_cmp_le0000_cy_3_CYSELG_3275
    );
  Mcompar_min_s_cmp_le0000_lut_3_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X38Y25"
    )
    port map (
      ADR0 => G_i_3_IBUF_1319,
      ADR1 => R_i_3_IBUF_1317,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0000_lut(3)
    );
  Mcompar_min_s_cmp_le0000_cy_5_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X38Y26"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0000_cy_5_CY0F_3329,
      IB => Mcompar_min_s_cmp_le0000_cy_5_CY0F_3329,
      SEL => Mcompar_min_s_cmp_le0000_cy_5_CYSELF_3320,
      O => Mcompar_min_s_cmp_le0000_cy_5_CYMUXF2_3315
    );
  Mcompar_min_s_cmp_le0000_cy_5_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X38Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_4_IBUF_1294,
      O => Mcompar_min_s_cmp_le0000_cy_5_CY0F_3329
    );
  Mcompar_min_s_cmp_le0000_cy_5_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X38Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0000_lut(4),
      O => Mcompar_min_s_cmp_le0000_cy_5_CYSELF_3320
    );
  Mcompar_min_s_cmp_le0000_cy_5_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X38Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0000_cy_3_CYMUXFAST_3288,
      O => Mcompar_min_s_cmp_le0000_cy_5_FASTCARRY_3317
    );
  Mcompar_min_s_cmp_le0000_cy_5_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X38Y26"
    )
    port map (
      I0 => Mcompar_min_s_cmp_le0000_cy_5_CYSELG_3306,
      I1 => Mcompar_min_s_cmp_le0000_cy_5_CYSELF_3320,
      O => Mcompar_min_s_cmp_le0000_cy_5_CYAND_3318
    );
  Mcompar_min_s_cmp_le0000_cy_5_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X38Y26"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0000_cy_5_CYMUXG2_3316,
      IB => Mcompar_min_s_cmp_le0000_cy_5_FASTCARRY_3317,
      SEL => Mcompar_min_s_cmp_le0000_cy_5_CYAND_3318,
      O => Mcompar_min_s_cmp_le0000_cy_5_CYMUXFAST_3319
    );
  Mcompar_min_s_cmp_le0000_cy_5_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X38Y26"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0000_cy_5_CY0G_3314,
      IB => Mcompar_min_s_cmp_le0000_cy_5_CYMUXF2_3315,
      SEL => Mcompar_min_s_cmp_le0000_cy_5_CYSELG_3306,
      O => Mcompar_min_s_cmp_le0000_cy_5_CYMUXG2_3316
    );
  Mcompar_min_s_cmp_le0000_cy_5_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X38Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_5_IBUF_1312,
      O => Mcompar_min_s_cmp_le0000_cy_5_CY0G_3314
    );
  Mcompar_min_s_cmp_le0000_cy_5_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X38Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0000_lut(5),
      O => Mcompar_min_s_cmp_le0000_cy_5_CYSELG_3306
    );
  Mcompar_min_s_cmp_le0000_lut_5_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X38Y26"
    )
    port map (
      ADR0 => R_i_5_IBUF_1313,
      ADR1 => G_i_5_IBUF_1312,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0000_lut(5)
    );
  min_s_cmp_le0000_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X38Y27"
    )
    port map (
      IA => min_s_cmp_le0000_CY0F_3360,
      IB => min_s_cmp_le0000_CY0F_3360,
      SEL => min_s_cmp_le0000_CYSELF_3351,
      O => min_s_cmp_le0000_CYMUXF2_3346
    );
  min_s_cmp_le0000_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X38Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_6_IBUF_1307,
      O => min_s_cmp_le0000_CY0F_3360
    );
  min_s_cmp_le0000_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X38Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0000_lut(6),
      O => min_s_cmp_le0000_CYSELF_3351
    );
  min_s_cmp_le0000_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X38Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => min_s_cmp_le0000_CYMUXFAST_3350,
      O => min_s_cmp_le0000
    );
  min_s_cmp_le0000_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X38Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0000_cy_5_CYMUXFAST_3319,
      O => min_s_cmp_le0000_FASTCARRY_3348
    );
  min_s_cmp_le0000_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X38Y27"
    )
    port map (
      I0 => min_s_cmp_le0000_CYSELG_3337,
      I1 => min_s_cmp_le0000_CYSELF_3351,
      O => min_s_cmp_le0000_CYAND_3349
    );
  min_s_cmp_le0000_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X38Y27"
    )
    port map (
      IA => min_s_cmp_le0000_CYMUXG2_3347,
      IB => min_s_cmp_le0000_FASTCARRY_3348,
      SEL => min_s_cmp_le0000_CYAND_3349,
      O => min_s_cmp_le0000_CYMUXFAST_3350
    );
  min_s_cmp_le0000_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X38Y27"
    )
    port map (
      IA => min_s_cmp_le0000_CY0G_3345,
      IB => min_s_cmp_le0000_CYMUXF2_3346,
      SEL => min_s_cmp_le0000_CYSELG_3337,
      O => min_s_cmp_le0000_CYMUXG2_3347
    );
  min_s_cmp_le0000_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X38Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_7_IBUF_1275,
      O => min_s_cmp_le0000_CY0G_3345
    );
  min_s_cmp_le0000_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X38Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0000_lut(7),
      O => min_s_cmp_le0000_CYSELG_3337
    );
  Mcompar_min_s_cmp_le0000_lut_7_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X38Y27"
    )
    port map (
      ADR0 => G_i_7_IBUF_1275,
      ADR1 => R_i_7_IBUF_1271,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0000_lut(7)
    );
  Madd_Y_large_s_addsub0000_Madd_lut_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y18",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(0),
      O => Madd_Y_large_s_addsub0000_Madd_lut_0_0
    );
  Madd_Y_large_s_addsub0000_Madd_lut_0_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X34Y18"
    )
    port map (
      IA => Madd_Y_large_s_addsub0000_Madd_lut_0_CY0F_3393,
      IB => Madd_Y_large_s_addsub0000_Madd_lut_0_CYINIT_3394,
      SEL => Madd_Y_large_s_addsub0000_Madd_lut_0_CYSELF_3385,
      O => Madd_Y_large_s_addsub0000_Madd_cy(0)
    );
  Madd_Y_large_s_addsub0000_Madd_lut_0_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X34Y18",
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => Madd_Y_large_s_addsub0000_Madd_lut_0_CYINIT_3394
    );
  Madd_Y_large_s_addsub0000_Madd_lut_0_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X34Y18",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_output_s(0),
      O => Madd_Y_large_s_addsub0000_Madd_lut_0_CY0F_3393
    );
  Madd_Y_large_s_addsub0000_Madd_lut_0_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X34Y18",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(0),
      O => Madd_Y_large_s_addsub0000_Madd_lut_0_CYSELF_3385
    );
  Madd_Y_large_s_addsub0000_Madd_lut_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y18",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut_0_XORG_3381,
      O => Y_large_s_addsub0000(1)
    );
  Madd_Y_large_s_addsub0000_Madd_lut_0_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X34Y18"
    )
    port map (
      I0 => Madd_Y_large_s_addsub0000_Madd_cy(0),
      I1 => Madd_Y_large_s_addsub0000_Madd_lut(1),
      O => Madd_Y_large_s_addsub0000_Madd_lut_0_XORG_3381
    );
  Madd_Y_large_s_addsub0000_Madd_lut_0_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y18",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut_0_CYMUXG_3380,
      O => Madd_Y_large_s_addsub0000_Madd_cy(1)
    );
  Madd_Y_large_s_addsub0000_Madd_lut_0_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X34Y18"
    )
    port map (
      IA => Madd_Y_large_s_addsub0000_Madd_lut_0_CY0G_3378,
      IB => Madd_Y_large_s_addsub0000_Madd_cy(0),
      SEL => Madd_Y_large_s_addsub0000_Madd_lut_0_CYSELG_3370,
      O => Madd_Y_large_s_addsub0000_Madd_lut_0_CYMUXG_3380
    );
  Madd_Y_large_s_addsub0000_Madd_lut_0_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X34Y18",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_output_s(1),
      O => Madd_Y_large_s_addsub0000_Madd_lut_0_CY0G_3378
    );
  Madd_Y_large_s_addsub0000_Madd_lut_0_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X34Y18",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(1),
      O => Madd_Y_large_s_addsub0000_Madd_lut_0_CYSELG_3370
    );
  Madd_Y_large_s_addsub0000_Madd_lut_1_Q : X_LUT4
    generic map(
      INIT => X"33CC",
      LOC => "SLICE_X34Y18"
    )
    port map (
      ADR0 => VCC,
      ADR1 => R_output_s(1),
      ADR2 => VCC,
      ADR3 => G_output_s(1),
      O => Madd_Y_large_s_addsub0000_Madd_lut(1)
    );
  Y_large_s_addsub0000_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y19",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_2_XORF_3433,
      O => Y_large_s_addsub0000(2)
    );
  Y_large_s_addsub0000_2_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X34Y19"
    )
    port map (
      I0 => Y_large_s_addsub0000_2_CYINIT_3432,
      I1 => Madd_Y_large_s_addsub0000_Madd_lut(2),
      O => Y_large_s_addsub0000_2_XORF_3433
    );
  Y_large_s_addsub0000_2_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X34Y19"
    )
    port map (
      IA => Y_large_s_addsub0000_2_CY0F_3431,
      IB => Y_large_s_addsub0000_2_CYINIT_3432,
      SEL => Y_large_s_addsub0000_2_CYSELF_3419,
      O => Madd_Y_large_s_addsub0000_Madd_cy(2)
    );
  Y_large_s_addsub0000_2_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X34Y19"
    )
    port map (
      IA => Y_large_s_addsub0000_2_CY0F_3431,
      IB => Y_large_s_addsub0000_2_CY0F_3431,
      SEL => Y_large_s_addsub0000_2_CYSELF_3419,
      O => Y_large_s_addsub0000_2_CYMUXF2_3414
    );
  Y_large_s_addsub0000_2_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X34Y19",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_cy(1),
      O => Y_large_s_addsub0000_2_CYINIT_3432
    );
  Y_large_s_addsub0000_2_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X34Y19",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_output_s(2),
      O => Y_large_s_addsub0000_2_CY0F_3431
    );
  Y_large_s_addsub0000_2_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X34Y19",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(2),
      O => Y_large_s_addsub0000_2_CYSELF_3419
    );
  Y_large_s_addsub0000_2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y19",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_2_XORG_3421,
      O => Y_large_s_addsub0000(3)
    );
  Y_large_s_addsub0000_2_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X34Y19"
    )
    port map (
      I0 => Madd_Y_large_s_addsub0000_Madd_cy(2),
      I1 => Madd_Y_large_s_addsub0000_Madd_lut(3),
      O => Y_large_s_addsub0000_2_XORG_3421
    );
  Y_large_s_addsub0000_2_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y19",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_2_CYMUXFAST_3418,
      O => Madd_Y_large_s_addsub0000_Madd_cy(3)
    );
  Y_large_s_addsub0000_2_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X34Y19",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_cy(1),
      O => Y_large_s_addsub0000_2_FASTCARRY_3416
    );
  Y_large_s_addsub0000_2_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X34Y19"
    )
    port map (
      I0 => Y_large_s_addsub0000_2_CYSELG_3405,
      I1 => Y_large_s_addsub0000_2_CYSELF_3419,
      O => Y_large_s_addsub0000_2_CYAND_3417
    );
  Y_large_s_addsub0000_2_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X34Y19"
    )
    port map (
      IA => Y_large_s_addsub0000_2_CYMUXG2_3415,
      IB => Y_large_s_addsub0000_2_FASTCARRY_3416,
      SEL => Y_large_s_addsub0000_2_CYAND_3417,
      O => Y_large_s_addsub0000_2_CYMUXFAST_3418
    );
  Y_large_s_addsub0000_2_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X34Y19"
    )
    port map (
      IA => Y_large_s_addsub0000_2_CY0G_3413,
      IB => Y_large_s_addsub0000_2_CYMUXF2_3414,
      SEL => Y_large_s_addsub0000_2_CYSELG_3405,
      O => Y_large_s_addsub0000_2_CYMUXG2_3415
    );
  Y_large_s_addsub0000_2_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X34Y19",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_output_s(3),
      O => Y_large_s_addsub0000_2_CY0G_3413
    );
  Y_large_s_addsub0000_2_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X34Y19",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(3),
      O => Y_large_s_addsub0000_2_CYSELG_3405
    );
  Madd_Y_large_s_addsub0000_Madd_lut_3_Q : X_LUT4
    generic map(
      INIT => X"55AA",
      LOC => "SLICE_X34Y19"
    )
    port map (
      ADR0 => R_output_s(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => G_output_s(3),
      O => Madd_Y_large_s_addsub0000_Madd_lut(3)
    );
  Y_large_s_addsub0000_4_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_4_XORF_3472,
      O => Y_large_s_addsub0000(4)
    );
  Y_large_s_addsub0000_4_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X34Y20"
    )
    port map (
      I0 => Y_large_s_addsub0000_4_CYINIT_3471,
      I1 => Madd_Y_large_s_addsub0000_Madd_lut(4),
      O => Y_large_s_addsub0000_4_XORF_3472
    );
  Y_large_s_addsub0000_4_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X34Y20"
    )
    port map (
      IA => Y_large_s_addsub0000_4_CY0F_3470,
      IB => Y_large_s_addsub0000_4_CYINIT_3471,
      SEL => Y_large_s_addsub0000_4_CYSELF_3458,
      O => Madd_Y_large_s_addsub0000_Madd_cy(4)
    );
  Y_large_s_addsub0000_4_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X34Y20"
    )
    port map (
      IA => Y_large_s_addsub0000_4_CY0F_3470,
      IB => Y_large_s_addsub0000_4_CY0F_3470,
      SEL => Y_large_s_addsub0000_4_CYSELF_3458,
      O => Y_large_s_addsub0000_4_CYMUXF2_3453
    );
  Y_large_s_addsub0000_4_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X34Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_cy(3),
      O => Y_large_s_addsub0000_4_CYINIT_3471
    );
  Y_large_s_addsub0000_4_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X34Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_output_s(4),
      O => Y_large_s_addsub0000_4_CY0F_3470
    );
  Y_large_s_addsub0000_4_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X34Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(4),
      O => Y_large_s_addsub0000_4_CYSELF_3458
    );
  Y_large_s_addsub0000_4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_4_XORG_3460,
      O => Y_large_s_addsub0000(5)
    );
  Y_large_s_addsub0000_4_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X34Y20"
    )
    port map (
      I0 => Madd_Y_large_s_addsub0000_Madd_cy(4),
      I1 => Madd_Y_large_s_addsub0000_Madd_lut(5),
      O => Y_large_s_addsub0000_4_XORG_3460
    );
  Y_large_s_addsub0000_4_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_4_CYMUXFAST_3457,
      O => Madd_Y_large_s_addsub0000_Madd_cy(5)
    );
  Y_large_s_addsub0000_4_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X34Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_cy(3),
      O => Y_large_s_addsub0000_4_FASTCARRY_3455
    );
  Y_large_s_addsub0000_4_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X34Y20"
    )
    port map (
      I0 => Y_large_s_addsub0000_4_CYSELG_3444,
      I1 => Y_large_s_addsub0000_4_CYSELF_3458,
      O => Y_large_s_addsub0000_4_CYAND_3456
    );
  Y_large_s_addsub0000_4_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X34Y20"
    )
    port map (
      IA => Y_large_s_addsub0000_4_CYMUXG2_3454,
      IB => Y_large_s_addsub0000_4_FASTCARRY_3455,
      SEL => Y_large_s_addsub0000_4_CYAND_3456,
      O => Y_large_s_addsub0000_4_CYMUXFAST_3457
    );
  Y_large_s_addsub0000_4_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X34Y20"
    )
    port map (
      IA => Y_large_s_addsub0000_4_CY0G_3452,
      IB => Y_large_s_addsub0000_4_CYMUXF2_3453,
      SEL => Y_large_s_addsub0000_4_CYSELG_3444,
      O => Y_large_s_addsub0000_4_CYMUXG2_3454
    );
  Y_large_s_addsub0000_4_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X34Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_output_s(5),
      O => Y_large_s_addsub0000_4_CY0G_3452
    );
  Y_large_s_addsub0000_4_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X34Y20",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(5),
      O => Y_large_s_addsub0000_4_CYSELG_3444
    );
  Madd_Y_large_s_addsub0000_Madd_lut_5_Q : X_LUT4
    generic map(
      INIT => X"6666",
      LOC => "SLICE_X34Y20"
    )
    port map (
      ADR0 => R_output_s(5),
      ADR1 => G_output_s(5),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Madd_Y_large_s_addsub0000_Madd_lut(5)
    );
  Y_large_s_addsub0000_6_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_6_XORF_3511,
      O => Y_large_s_addsub0000(6)
    );
  Y_large_s_addsub0000_6_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X34Y21"
    )
    port map (
      I0 => Y_large_s_addsub0000_6_CYINIT_3510,
      I1 => Madd_Y_large_s_addsub0000_Madd_lut(6),
      O => Y_large_s_addsub0000_6_XORF_3511
    );
  Y_large_s_addsub0000_6_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X34Y21"
    )
    port map (
      IA => Y_large_s_addsub0000_6_CY0F_3509,
      IB => Y_large_s_addsub0000_6_CYINIT_3510,
      SEL => Y_large_s_addsub0000_6_CYSELF_3497,
      O => Madd_Y_large_s_addsub0000_Madd_cy(6)
    );
  Y_large_s_addsub0000_6_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X34Y21"
    )
    port map (
      IA => Y_large_s_addsub0000_6_CY0F_3509,
      IB => Y_large_s_addsub0000_6_CY0F_3509,
      SEL => Y_large_s_addsub0000_6_CYSELF_3497,
      O => Y_large_s_addsub0000_6_CYMUXF2_3492
    );
  Y_large_s_addsub0000_6_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X34Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_cy(5),
      O => Y_large_s_addsub0000_6_CYINIT_3510
    );
  Y_large_s_addsub0000_6_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X34Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_output_s(6),
      O => Y_large_s_addsub0000_6_CY0F_3509
    );
  Y_large_s_addsub0000_6_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X34Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(6),
      O => Y_large_s_addsub0000_6_CYSELF_3497
    );
  Y_large_s_addsub0000_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_6_XORG_3499,
      O => Y_large_s_addsub0000(7)
    );
  Y_large_s_addsub0000_6_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X34Y21"
    )
    port map (
      I0 => Madd_Y_large_s_addsub0000_Madd_cy(6),
      I1 => Madd_Y_large_s_addsub0000_Madd_lut(7),
      O => Y_large_s_addsub0000_6_XORG_3499
    );
  Y_large_s_addsub0000_6_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_6_CYMUXFAST_3496,
      O => Madd_Y_large_s_addsub0000_Madd_cy(7)
    );
  Y_large_s_addsub0000_6_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X34Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_cy(5),
      O => Y_large_s_addsub0000_6_FASTCARRY_3494
    );
  Y_large_s_addsub0000_6_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X34Y21"
    )
    port map (
      I0 => Y_large_s_addsub0000_6_CYSELG_3483,
      I1 => Y_large_s_addsub0000_6_CYSELF_3497,
      O => Y_large_s_addsub0000_6_CYAND_3495
    );
  Y_large_s_addsub0000_6_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X34Y21"
    )
    port map (
      IA => Y_large_s_addsub0000_6_CYMUXG2_3493,
      IB => Y_large_s_addsub0000_6_FASTCARRY_3494,
      SEL => Y_large_s_addsub0000_6_CYAND_3495,
      O => Y_large_s_addsub0000_6_CYMUXFAST_3496
    );
  Y_large_s_addsub0000_6_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X34Y21"
    )
    port map (
      IA => Y_large_s_addsub0000_6_CY0G_3491,
      IB => Y_large_s_addsub0000_6_CYMUXF2_3492,
      SEL => Y_large_s_addsub0000_6_CYSELG_3483,
      O => Y_large_s_addsub0000_6_CYMUXG2_3493
    );
  Y_large_s_addsub0000_6_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X34Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_output_s(7),
      O => Y_large_s_addsub0000_6_CY0G_3491
    );
  Y_large_s_addsub0000_6_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X34Y21",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(7),
      O => Y_large_s_addsub0000_6_CYSELG_3483
    );
  Madd_Y_large_s_addsub0000_Madd_lut_7_Q : X_LUT4
    generic map(
      INIT => X"6666",
      LOC => "SLICE_X34Y21"
    )
    port map (
      ADR0 => G_output_s(7),
      ADR1 => R_output_s(7),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Madd_Y_large_s_addsub0000_Madd_lut(7)
    );
  Y_large_s_addsub0000_8_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_8_XORF_3550,
      O => Y_large_s_addsub0000(8)
    );
  Y_large_s_addsub0000_8_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X34Y22"
    )
    port map (
      I0 => Y_large_s_addsub0000_8_CYINIT_3549,
      I1 => Madd_Y_large_s_addsub0000_Madd_lut(8),
      O => Y_large_s_addsub0000_8_XORF_3550
    );
  Y_large_s_addsub0000_8_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X34Y22"
    )
    port map (
      IA => Y_large_s_addsub0000_8_CY0F_3548,
      IB => Y_large_s_addsub0000_8_CYINIT_3549,
      SEL => Y_large_s_addsub0000_8_CYSELF_3536,
      O => Madd_Y_large_s_addsub0000_Madd_cy(8)
    );
  Y_large_s_addsub0000_8_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X34Y22"
    )
    port map (
      IA => Y_large_s_addsub0000_8_CY0F_3548,
      IB => Y_large_s_addsub0000_8_CY0F_3548,
      SEL => Y_large_s_addsub0000_8_CYSELF_3536,
      O => Y_large_s_addsub0000_8_CYMUXF2_3531
    );
  Y_large_s_addsub0000_8_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X34Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_cy(7),
      O => Y_large_s_addsub0000_8_CYINIT_3549
    );
  Y_large_s_addsub0000_8_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X34Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_output_s(8),
      O => Y_large_s_addsub0000_8_CY0F_3548
    );
  Y_large_s_addsub0000_8_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X34Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(8),
      O => Y_large_s_addsub0000_8_CYSELF_3536
    );
  Y_large_s_addsub0000_8_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_8_XORG_3538,
      O => Y_large_s_addsub0000(9)
    );
  Y_large_s_addsub0000_8_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X34Y22"
    )
    port map (
      I0 => Madd_Y_large_s_addsub0000_Madd_cy(8),
      I1 => Madd_Y_large_s_addsub0000_Madd_lut(9),
      O => Y_large_s_addsub0000_8_XORG_3538
    );
  Y_large_s_addsub0000_8_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_8_CYMUXFAST_3535,
      O => Madd_Y_large_s_addsub0000_Madd_cy(9)
    );
  Y_large_s_addsub0000_8_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X34Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_cy(7),
      O => Y_large_s_addsub0000_8_FASTCARRY_3533
    );
  Y_large_s_addsub0000_8_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X34Y22"
    )
    port map (
      I0 => Y_large_s_addsub0000_8_CYSELG_3522,
      I1 => Y_large_s_addsub0000_8_CYSELF_3536,
      O => Y_large_s_addsub0000_8_CYAND_3534
    );
  Y_large_s_addsub0000_8_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X34Y22"
    )
    port map (
      IA => Y_large_s_addsub0000_8_CYMUXG2_3532,
      IB => Y_large_s_addsub0000_8_FASTCARRY_3533,
      SEL => Y_large_s_addsub0000_8_CYAND_3534,
      O => Y_large_s_addsub0000_8_CYMUXFAST_3535
    );
  Y_large_s_addsub0000_8_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X34Y22"
    )
    port map (
      IA => Y_large_s_addsub0000_8_CY0G_3530,
      IB => Y_large_s_addsub0000_8_CYMUXF2_3531,
      SEL => Y_large_s_addsub0000_8_CYSELG_3522,
      O => Y_large_s_addsub0000_8_CYMUXG2_3532
    );
  Y_large_s_addsub0000_8_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X34Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_output_s(9),
      O => Y_large_s_addsub0000_8_CY0G_3530
    );
  Y_large_s_addsub0000_8_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X34Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(9),
      O => Y_large_s_addsub0000_8_CYSELG_3522
    );
  Madd_Y_large_s_addsub0000_Madd_lut_9_Q : X_LUT4
    generic map(
      INIT => X"55AA",
      LOC => "SLICE_X34Y22"
    )
    port map (
      ADR0 => R_output_s(9),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => G_output_s(9),
      O => Madd_Y_large_s_addsub0000_Madd_lut(9)
    );
  Y_large_s_addsub0000_10_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_10_XORF_3589,
      O => Y_large_s_addsub0000(10)
    );
  Y_large_s_addsub0000_10_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X34Y23"
    )
    port map (
      I0 => Y_large_s_addsub0000_10_CYINIT_3588,
      I1 => Madd_Y_large_s_addsub0000_Madd_lut(10),
      O => Y_large_s_addsub0000_10_XORF_3589
    );
  Y_large_s_addsub0000_10_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X34Y23"
    )
    port map (
      IA => Y_large_s_addsub0000_10_CY0F_3587,
      IB => Y_large_s_addsub0000_10_CYINIT_3588,
      SEL => Y_large_s_addsub0000_10_CYSELF_3575,
      O => Madd_Y_large_s_addsub0000_Madd_cy(10)
    );
  Y_large_s_addsub0000_10_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X34Y23"
    )
    port map (
      IA => Y_large_s_addsub0000_10_CY0F_3587,
      IB => Y_large_s_addsub0000_10_CY0F_3587,
      SEL => Y_large_s_addsub0000_10_CYSELF_3575,
      O => Y_large_s_addsub0000_10_CYMUXF2_3570
    );
  Y_large_s_addsub0000_10_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X34Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_cy(9),
      O => Y_large_s_addsub0000_10_CYINIT_3588
    );
  Y_large_s_addsub0000_10_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X34Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_output_s(10),
      O => Y_large_s_addsub0000_10_CY0F_3587
    );
  Y_large_s_addsub0000_10_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X34Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(10),
      O => Y_large_s_addsub0000_10_CYSELF_3575
    );
  Y_large_s_addsub0000_10_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_10_XORG_3577,
      O => Y_large_s_addsub0000(11)
    );
  Y_large_s_addsub0000_10_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X34Y23"
    )
    port map (
      I0 => Madd_Y_large_s_addsub0000_Madd_cy(10),
      I1 => Madd_Y_large_s_addsub0000_Madd_lut(11),
      O => Y_large_s_addsub0000_10_XORG_3577
    );
  Y_large_s_addsub0000_10_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_10_CYMUXFAST_3574,
      O => Madd_Y_large_s_addsub0000_Madd_cy(11)
    );
  Y_large_s_addsub0000_10_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X34Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_cy(9),
      O => Y_large_s_addsub0000_10_FASTCARRY_3572
    );
  Y_large_s_addsub0000_10_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X34Y23"
    )
    port map (
      I0 => Y_large_s_addsub0000_10_CYSELG_3561,
      I1 => Y_large_s_addsub0000_10_CYSELF_3575,
      O => Y_large_s_addsub0000_10_CYAND_3573
    );
  Y_large_s_addsub0000_10_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X34Y23"
    )
    port map (
      IA => Y_large_s_addsub0000_10_CYMUXG2_3571,
      IB => Y_large_s_addsub0000_10_FASTCARRY_3572,
      SEL => Y_large_s_addsub0000_10_CYAND_3573,
      O => Y_large_s_addsub0000_10_CYMUXFAST_3574
    );
  Y_large_s_addsub0000_10_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X34Y23"
    )
    port map (
      IA => Y_large_s_addsub0000_10_CY0G_3569,
      IB => Y_large_s_addsub0000_10_CYMUXF2_3570,
      SEL => Y_large_s_addsub0000_10_CYSELG_3561,
      O => Y_large_s_addsub0000_10_CYMUXG2_3571
    );
  Y_large_s_addsub0000_10_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X34Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_output_s(11),
      O => Y_large_s_addsub0000_10_CY0G_3569
    );
  Y_large_s_addsub0000_10_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X34Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(11),
      O => Y_large_s_addsub0000_10_CYSELG_3561
    );
  Madd_Y_large_s_addsub0000_Madd_lut_11_Q : X_LUT4
    generic map(
      INIT => X"6666",
      LOC => "SLICE_X34Y23"
    )
    port map (
      ADR0 => R_output_s(11),
      ADR1 => G_output_s(11),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Madd_Y_large_s_addsub0000_Madd_lut(11)
    );
  Y_large_s_addsub0000_12_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_12_XORF_3628,
      O => Y_large_s_addsub0000(12)
    );
  Y_large_s_addsub0000_12_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X34Y24"
    )
    port map (
      I0 => Y_large_s_addsub0000_12_CYINIT_3627,
      I1 => Madd_Y_large_s_addsub0000_Madd_lut(12),
      O => Y_large_s_addsub0000_12_XORF_3628
    );
  Y_large_s_addsub0000_12_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X34Y24"
    )
    port map (
      IA => Y_large_s_addsub0000_12_CY0F_3626,
      IB => Y_large_s_addsub0000_12_CYINIT_3627,
      SEL => Y_large_s_addsub0000_12_CYSELF_3614,
      O => Madd_Y_large_s_addsub0000_Madd_cy(12)
    );
  Y_large_s_addsub0000_12_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X34Y24"
    )
    port map (
      IA => Y_large_s_addsub0000_12_CY0F_3626,
      IB => Y_large_s_addsub0000_12_CY0F_3626,
      SEL => Y_large_s_addsub0000_12_CYSELF_3614,
      O => Y_large_s_addsub0000_12_CYMUXF2_3609
    );
  Y_large_s_addsub0000_12_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X34Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_cy(11),
      O => Y_large_s_addsub0000_12_CYINIT_3627
    );
  Y_large_s_addsub0000_12_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X34Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_output_s(12),
      O => Y_large_s_addsub0000_12_CY0F_3626
    );
  Y_large_s_addsub0000_12_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X34Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(12),
      O => Y_large_s_addsub0000_12_CYSELF_3614
    );
  Y_large_s_addsub0000_12_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_12_XORG_3616,
      O => Y_large_s_addsub0000(13)
    );
  Y_large_s_addsub0000_12_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X34Y24"
    )
    port map (
      I0 => Madd_Y_large_s_addsub0000_Madd_cy(12),
      I1 => Madd_Y_large_s_addsub0000_Madd_lut(13),
      O => Y_large_s_addsub0000_12_XORG_3616
    );
  Y_large_s_addsub0000_12_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_12_CYMUXFAST_3613,
      O => Madd_Y_large_s_addsub0000_Madd_cy(13)
    );
  Y_large_s_addsub0000_12_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X34Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_cy(11),
      O => Y_large_s_addsub0000_12_FASTCARRY_3611
    );
  Y_large_s_addsub0000_12_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X34Y24"
    )
    port map (
      I0 => Y_large_s_addsub0000_12_CYSELG_3600,
      I1 => Y_large_s_addsub0000_12_CYSELF_3614,
      O => Y_large_s_addsub0000_12_CYAND_3612
    );
  Y_large_s_addsub0000_12_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X34Y24"
    )
    port map (
      IA => Y_large_s_addsub0000_12_CYMUXG2_3610,
      IB => Y_large_s_addsub0000_12_FASTCARRY_3611,
      SEL => Y_large_s_addsub0000_12_CYAND_3612,
      O => Y_large_s_addsub0000_12_CYMUXFAST_3613
    );
  Y_large_s_addsub0000_12_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X34Y24"
    )
    port map (
      IA => Y_large_s_addsub0000_12_CY0G_3608,
      IB => Y_large_s_addsub0000_12_CYMUXF2_3609,
      SEL => Y_large_s_addsub0000_12_CYSELG_3600,
      O => Y_large_s_addsub0000_12_CYMUXG2_3610
    );
  Y_large_s_addsub0000_12_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X34Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_output_s(13),
      O => Y_large_s_addsub0000_12_CY0G_3608
    );
  Y_large_s_addsub0000_12_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X34Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(13),
      O => Y_large_s_addsub0000_12_CYSELG_3600
    );
  Madd_Y_large_s_addsub0000_Madd_lut_13_Q : X_LUT4
    generic map(
      INIT => X"5A5A",
      LOC => "SLICE_X34Y24"
    )
    port map (
      ADR0 => R_output_s(13),
      ADR1 => VCC,
      ADR2 => G_output_s(13),
      ADR3 => VCC,
      O => Madd_Y_large_s_addsub0000_Madd_lut(13)
    );
  Y_large_s_addsub0000_14_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_14_XORF_3667,
      O => Y_large_s_addsub0000(14)
    );
  Y_large_s_addsub0000_14_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X34Y25"
    )
    port map (
      I0 => Y_large_s_addsub0000_14_CYINIT_3666,
      I1 => Madd_Y_large_s_addsub0000_Madd_lut(14),
      O => Y_large_s_addsub0000_14_XORF_3667
    );
  Y_large_s_addsub0000_14_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X34Y25"
    )
    port map (
      IA => Y_large_s_addsub0000_14_CY0F_3665,
      IB => Y_large_s_addsub0000_14_CYINIT_3666,
      SEL => Y_large_s_addsub0000_14_CYSELF_3653,
      O => Madd_Y_large_s_addsub0000_Madd_cy(14)
    );
  Y_large_s_addsub0000_14_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X34Y25"
    )
    port map (
      IA => Y_large_s_addsub0000_14_CY0F_3665,
      IB => Y_large_s_addsub0000_14_CY0F_3665,
      SEL => Y_large_s_addsub0000_14_CYSELF_3653,
      O => Y_large_s_addsub0000_14_CYMUXF2_3648
    );
  Y_large_s_addsub0000_14_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X34Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_cy(13),
      O => Y_large_s_addsub0000_14_CYINIT_3666
    );
  Y_large_s_addsub0000_14_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X34Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_output_s(14),
      O => Y_large_s_addsub0000_14_CY0F_3665
    );
  Y_large_s_addsub0000_14_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X34Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(14),
      O => Y_large_s_addsub0000_14_CYSELF_3653
    );
  Y_large_s_addsub0000_14_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_14_XORG_3655,
      O => Y_large_s_addsub0000(15)
    );
  Y_large_s_addsub0000_14_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X34Y25"
    )
    port map (
      I0 => Madd_Y_large_s_addsub0000_Madd_cy(14),
      I1 => Madd_Y_large_s_addsub0000_Madd_lut(15),
      O => Y_large_s_addsub0000_14_XORG_3655
    );
  Y_large_s_addsub0000_14_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X34Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_cy(13),
      O => Y_large_s_addsub0000_14_FASTCARRY_3650
    );
  Y_large_s_addsub0000_14_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X34Y25"
    )
    port map (
      I0 => Y_large_s_addsub0000_14_CYSELG_3639,
      I1 => Y_large_s_addsub0000_14_CYSELF_3653,
      O => Y_large_s_addsub0000_14_CYAND_3651
    );
  Y_large_s_addsub0000_14_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X34Y25"
    )
    port map (
      IA => Y_large_s_addsub0000_14_CYMUXG2_3649,
      IB => Y_large_s_addsub0000_14_FASTCARRY_3650,
      SEL => Y_large_s_addsub0000_14_CYAND_3651,
      O => Y_large_s_addsub0000_14_CYMUXFAST_3652
    );
  Y_large_s_addsub0000_14_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X34Y25"
    )
    port map (
      IA => Y_large_s_addsub0000_14_CY0G_3647,
      IB => Y_large_s_addsub0000_14_CYMUXF2_3648,
      SEL => Y_large_s_addsub0000_14_CYSELG_3639,
      O => Y_large_s_addsub0000_14_CYMUXG2_3649
    );
  Y_large_s_addsub0000_14_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X34Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_output_s(15),
      O => Y_large_s_addsub0000_14_CY0G_3647
    );
  Y_large_s_addsub0000_14_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X34Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Madd_Y_large_s_addsub0000_Madd_lut(15),
      O => Y_large_s_addsub0000_14_CYSELG_3639
    );
  Madd_Y_large_s_addsub0000_Madd_lut_15_Q : X_LUT4
    generic map(
      INIT => X"55AA",
      LOC => "SLICE_X34Y25"
    )
    port map (
      ADR0 => R_output_s(15),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => G_output_s(15),
      O => Madd_Y_large_s_addsub0000_Madd_lut(15)
    );
  Y_large_s_addsub0000_16_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X34Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_16_XORF_3682,
      O => Y_large_s_addsub0000(16)
    );
  Y_large_s_addsub0000_16_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X34Y26"
    )
    port map (
      I0 => Y_large_s_addsub0000_16_CYINIT_3681,
      I1 => Madd_Y_large_s_addsub0000_Madd_lut(16),
      O => Y_large_s_addsub0000_16_XORF_3682
    );
  Y_large_s_addsub0000_16_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X34Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_addsub0000_14_CYMUXFAST_3652,
      O => Y_large_s_addsub0000_16_CYINIT_3681
    );
  Madd_Y_large_s_addsub0000_Madd_lut_16_Q : X_LUT4
    generic map(
      INIT => X"55AA",
      LOC => "SLICE_X34Y26"
    )
    port map (
      ADR0 => R_output_s(16),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => G_output_s(16),
      O => Madd_Y_large_s_addsub0000_Madd_lut(16)
    );
  Mcompar_offset_s_cmp_ge0003_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X29Y26"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0003_cy_1_CY0F_3712,
      IB => Mcompar_offset_s_cmp_ge0003_cy_1_CYINIT_3713,
      SEL => Mcompar_offset_s_cmp_ge0003_cy_1_CYSELF_3704,
      O => Mcompar_offset_s_cmp_ge0003_cy(0)
    );
  Mcompar_offset_s_cmp_ge0003_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X29Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => Mcompar_offset_s_cmp_ge0003_cy_1_CYINIT_3713
    );
  Mcompar_offset_s_cmp_ge0003_cy_1_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X29Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_0_IBUF_1300,
      O => Mcompar_offset_s_cmp_ge0003_cy_1_CY0F_3712
    );
  Mcompar_offset_s_cmp_ge0003_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X29Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0003_lut(0),
      O => Mcompar_offset_s_cmp_ge0003_cy_1_CYSELF_3704
    );
  Mcompar_offset_s_cmp_ge0003_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X29Y26"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0003_cy_1_CY0G_3699,
      IB => Mcompar_offset_s_cmp_ge0003_cy(0),
      SEL => Mcompar_offset_s_cmp_ge0003_cy_1_CYSELG_3691,
      O => Mcompar_offset_s_cmp_ge0003_cy_1_CYMUXG_3701
    );
  Mcompar_offset_s_cmp_ge0003_cy_1_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X29Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_1_IBUF_1287,
      O => Mcompar_offset_s_cmp_ge0003_cy_1_CY0G_3699
    );
  Mcompar_offset_s_cmp_ge0003_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X29Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0003_lut(1),
      O => Mcompar_offset_s_cmp_ge0003_cy_1_CYSELG_3691
    );
  Mcompar_offset_s_cmp_ge0003_lut_1_Q : X_LUT4
    generic map(
      INIT => X"C3C3",
      LOC => "SLICE_X29Y26"
    )
    port map (
      ADR0 => VCC,
      ADR1 => G_i_1_IBUF_1287,
      ADR2 => R_i_1_IBUF_1288,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0003_lut(1)
    );
  Mcompar_offset_s_cmp_ge0003_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X29Y27"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0003_cy_3_CY0F_3744,
      IB => Mcompar_offset_s_cmp_ge0003_cy_3_CY0F_3744,
      SEL => Mcompar_offset_s_cmp_ge0003_cy_3_CYSELF_3735,
      O => Mcompar_offset_s_cmp_ge0003_cy_3_CYMUXF2_3730
    );
  Mcompar_offset_s_cmp_ge0003_cy_3_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X29Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_2_IBUF_1284,
      O => Mcompar_offset_s_cmp_ge0003_cy_3_CY0F_3744
    );
  Mcompar_offset_s_cmp_ge0003_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X29Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0003_lut(2),
      O => Mcompar_offset_s_cmp_ge0003_cy_3_CYSELF_3735
    );
  Mcompar_offset_s_cmp_ge0003_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X29Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0003_cy_1_CYMUXG_3701,
      O => Mcompar_offset_s_cmp_ge0003_cy_3_FASTCARRY_3732
    );
  Mcompar_offset_s_cmp_ge0003_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X29Y27"
    )
    port map (
      I0 => Mcompar_offset_s_cmp_ge0003_cy_3_CYSELG_3721,
      I1 => Mcompar_offset_s_cmp_ge0003_cy_3_CYSELF_3735,
      O => Mcompar_offset_s_cmp_ge0003_cy_3_CYAND_3733
    );
  Mcompar_offset_s_cmp_ge0003_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X29Y27"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0003_cy_3_CYMUXG2_3731,
      IB => Mcompar_offset_s_cmp_ge0003_cy_3_FASTCARRY_3732,
      SEL => Mcompar_offset_s_cmp_ge0003_cy_3_CYAND_3733,
      O => Mcompar_offset_s_cmp_ge0003_cy_3_CYMUXFAST_3734
    );
  Mcompar_offset_s_cmp_ge0003_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X29Y27"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0003_cy_3_CY0G_3729,
      IB => Mcompar_offset_s_cmp_ge0003_cy_3_CYMUXF2_3730,
      SEL => Mcompar_offset_s_cmp_ge0003_cy_3_CYSELG_3721,
      O => Mcompar_offset_s_cmp_ge0003_cy_3_CYMUXG2_3731
    );
  Mcompar_offset_s_cmp_ge0003_cy_3_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X29Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_3_IBUF_1319,
      O => Mcompar_offset_s_cmp_ge0003_cy_3_CY0G_3729
    );
  Mcompar_offset_s_cmp_ge0003_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X29Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0003_lut(3),
      O => Mcompar_offset_s_cmp_ge0003_cy_3_CYSELG_3721
    );
  Mcompar_offset_s_cmp_ge0003_lut_3_Q : X_LUT4
    generic map(
      INIT => X"CC33",
      LOC => "SLICE_X29Y27"
    )
    port map (
      ADR0 => VCC,
      ADR1 => G_i_3_IBUF_1319,
      ADR2 => VCC,
      ADR3 => R_i_3_IBUF_1317,
      O => Mcompar_offset_s_cmp_ge0003_lut(3)
    );
  Mcompar_offset_s_cmp_ge0003_cy_5_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X29Y28"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0003_cy_5_CY0F_3775,
      IB => Mcompar_offset_s_cmp_ge0003_cy_5_CY0F_3775,
      SEL => Mcompar_offset_s_cmp_ge0003_cy_5_CYSELF_3766,
      O => Mcompar_offset_s_cmp_ge0003_cy_5_CYMUXF2_3761
    );
  Mcompar_offset_s_cmp_ge0003_cy_5_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X29Y28",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_4_IBUF_1294,
      O => Mcompar_offset_s_cmp_ge0003_cy_5_CY0F_3775
    );
  Mcompar_offset_s_cmp_ge0003_cy_5_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X29Y28",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0003_lut(4),
      O => Mcompar_offset_s_cmp_ge0003_cy_5_CYSELF_3766
    );
  Mcompar_offset_s_cmp_ge0003_cy_5_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X29Y28",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0003_cy_3_CYMUXFAST_3734,
      O => Mcompar_offset_s_cmp_ge0003_cy_5_FASTCARRY_3763
    );
  Mcompar_offset_s_cmp_ge0003_cy_5_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X29Y28"
    )
    port map (
      I0 => Mcompar_offset_s_cmp_ge0003_cy_5_CYSELG_3752,
      I1 => Mcompar_offset_s_cmp_ge0003_cy_5_CYSELF_3766,
      O => Mcompar_offset_s_cmp_ge0003_cy_5_CYAND_3764
    );
  Mcompar_offset_s_cmp_ge0003_cy_5_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X29Y28"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0003_cy_5_CYMUXG2_3762,
      IB => Mcompar_offset_s_cmp_ge0003_cy_5_FASTCARRY_3763,
      SEL => Mcompar_offset_s_cmp_ge0003_cy_5_CYAND_3764,
      O => Mcompar_offset_s_cmp_ge0003_cy_5_CYMUXFAST_3765
    );
  Mcompar_offset_s_cmp_ge0003_cy_5_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X29Y28"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0003_cy_5_CY0G_3760,
      IB => Mcompar_offset_s_cmp_ge0003_cy_5_CYMUXF2_3761,
      SEL => Mcompar_offset_s_cmp_ge0003_cy_5_CYSELG_3752,
      O => Mcompar_offset_s_cmp_ge0003_cy_5_CYMUXG2_3762
    );
  Mcompar_offset_s_cmp_ge0003_cy_5_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X29Y28",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_5_IBUF_1312,
      O => Mcompar_offset_s_cmp_ge0003_cy_5_CY0G_3760
    );
  Mcompar_offset_s_cmp_ge0003_cy_5_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X29Y28",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0003_lut(5),
      O => Mcompar_offset_s_cmp_ge0003_cy_5_CYSELG_3752
    );
  Mcompar_offset_s_cmp_ge0003_lut_5_Q : X_LUT4
    generic map(
      INIT => X"A5A5",
      LOC => "SLICE_X29Y28"
    )
    port map (
      ADR0 => G_i_5_IBUF_1312,
      ADR1 => VCC,
      ADR2 => R_i_5_IBUF_1313,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0003_lut(5)
    );
  offset_s_cmp_ge0003_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X29Y29"
    )
    port map (
      IA => offset_s_cmp_ge0003_CY0F_3806,
      IB => offset_s_cmp_ge0003_CY0F_3806,
      SEL => offset_s_cmp_ge0003_CYSELF_3797,
      O => offset_s_cmp_ge0003_CYMUXF2_3792
    );
  offset_s_cmp_ge0003_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X29Y29",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_6_IBUF_1307,
      O => offset_s_cmp_ge0003_CY0F_3806
    );
  offset_s_cmp_ge0003_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X29Y29",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0003_lut(6),
      O => offset_s_cmp_ge0003_CYSELF_3797
    );
  offset_s_cmp_ge0003_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y29",
      PATHPULSE => 757 ps
    )
    port map (
      I => offset_s_cmp_ge0003_CYMUXFAST_3796,
      O => offset_s_cmp_ge0003
    );
  offset_s_cmp_ge0003_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X29Y29",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0003_cy_5_CYMUXFAST_3765,
      O => offset_s_cmp_ge0003_FASTCARRY_3794
    );
  offset_s_cmp_ge0003_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X29Y29"
    )
    port map (
      I0 => offset_s_cmp_ge0003_CYSELG_3783,
      I1 => offset_s_cmp_ge0003_CYSELF_3797,
      O => offset_s_cmp_ge0003_CYAND_3795
    );
  offset_s_cmp_ge0003_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X29Y29"
    )
    port map (
      IA => offset_s_cmp_ge0003_CYMUXG2_3793,
      IB => offset_s_cmp_ge0003_FASTCARRY_3794,
      SEL => offset_s_cmp_ge0003_CYAND_3795,
      O => offset_s_cmp_ge0003_CYMUXFAST_3796
    );
  offset_s_cmp_ge0003_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X29Y29"
    )
    port map (
      IA => offset_s_cmp_ge0003_CY0G_3791,
      IB => offset_s_cmp_ge0003_CYMUXF2_3792,
      SEL => offset_s_cmp_ge0003_CYSELG_3783,
      O => offset_s_cmp_ge0003_CYMUXG2_3793
    );
  offset_s_cmp_ge0003_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X29Y29",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_7_IBUF_1275,
      O => offset_s_cmp_ge0003_CY0G_3791
    );
  offset_s_cmp_ge0003_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X29Y29",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0003_lut(7),
      O => offset_s_cmp_ge0003_CYSELG_3783
    );
  Mcompar_offset_s_cmp_ge0003_lut_7_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X29Y29"
    )
    port map (
      ADR0 => G_i_7_IBUF_1275,
      ADR1 => R_i_7_IBUF_1271,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0003_lut(7)
    );
  Mcompar_offset_s_cmp_ge0000_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X36Y26"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0000_cy_1_CY0F_3835,
      IB => Mcompar_offset_s_cmp_ge0000_cy_1_CYINIT_3836,
      SEL => Mcompar_offset_s_cmp_ge0000_cy_1_CYSELF_3827,
      O => Mcompar_offset_s_cmp_ge0000_cy(0)
    );
  Mcompar_offset_s_cmp_ge0000_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X36Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => Mcompar_offset_s_cmp_ge0000_cy_1_CYINIT_3836
    );
  Mcompar_offset_s_cmp_ge0000_cy_1_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X36Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_0_IBUF_1301,
      O => Mcompar_offset_s_cmp_ge0000_cy_1_CY0F_3835
    );
  Mcompar_offset_s_cmp_ge0000_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X36Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0000_lut(0),
      O => Mcompar_offset_s_cmp_ge0000_cy_1_CYSELF_3827
    );
  Mcompar_offset_s_cmp_ge0000_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X36Y26"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0000_cy_1_CY0G_3822,
      IB => Mcompar_offset_s_cmp_ge0000_cy(0),
      SEL => Mcompar_offset_s_cmp_ge0000_cy_1_CYSELG_3814,
      O => Mcompar_offset_s_cmp_ge0000_cy_1_CYMUXG_3824
    );
  Mcompar_offset_s_cmp_ge0000_cy_1_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X36Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_1_IBUF_1288,
      O => Mcompar_offset_s_cmp_ge0000_cy_1_CY0G_3822
    );
  Mcompar_offset_s_cmp_ge0000_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X36Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0000_lut(1),
      O => Mcompar_offset_s_cmp_ge0000_cy_1_CYSELG_3814
    );
  Mcompar_offset_s_cmp_ge0000_lut_1_Q : X_LUT4
    generic map(
      INIT => X"C3C3",
      LOC => "SLICE_X36Y26"
    )
    port map (
      ADR0 => VCC,
      ADR1 => R_i_1_IBUF_1288,
      ADR2 => G_i_1_IBUF_1287,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0000_lut(1)
    );
  Mcompar_offset_s_cmp_ge0000_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X36Y27"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0000_cy_3_CY0F_3867,
      IB => Mcompar_offset_s_cmp_ge0000_cy_3_CY0F_3867,
      SEL => Mcompar_offset_s_cmp_ge0000_cy_3_CYSELF_3858,
      O => Mcompar_offset_s_cmp_ge0000_cy_3_CYMUXF2_3853
    );
  Mcompar_offset_s_cmp_ge0000_cy_3_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X36Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_2_IBUF_1280,
      O => Mcompar_offset_s_cmp_ge0000_cy_3_CY0F_3867
    );
  Mcompar_offset_s_cmp_ge0000_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X36Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0000_lut(2),
      O => Mcompar_offset_s_cmp_ge0000_cy_3_CYSELF_3858
    );
  Mcompar_offset_s_cmp_ge0000_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X36Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0000_cy_1_CYMUXG_3824,
      O => Mcompar_offset_s_cmp_ge0000_cy_3_FASTCARRY_3855
    );
  Mcompar_offset_s_cmp_ge0000_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X36Y27"
    )
    port map (
      I0 => Mcompar_offset_s_cmp_ge0000_cy_3_CYSELG_3844,
      I1 => Mcompar_offset_s_cmp_ge0000_cy_3_CYSELF_3858,
      O => Mcompar_offset_s_cmp_ge0000_cy_3_CYAND_3856
    );
  Mcompar_offset_s_cmp_ge0000_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X36Y27"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0000_cy_3_CYMUXG2_3854,
      IB => Mcompar_offset_s_cmp_ge0000_cy_3_FASTCARRY_3855,
      SEL => Mcompar_offset_s_cmp_ge0000_cy_3_CYAND_3856,
      O => Mcompar_offset_s_cmp_ge0000_cy_3_CYMUXFAST_3857
    );
  Mcompar_offset_s_cmp_ge0000_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X36Y27"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0000_cy_3_CY0G_3852,
      IB => Mcompar_offset_s_cmp_ge0000_cy_3_CYMUXF2_3853,
      SEL => Mcompar_offset_s_cmp_ge0000_cy_3_CYSELG_3844,
      O => Mcompar_offset_s_cmp_ge0000_cy_3_CYMUXG2_3854
    );
  Mcompar_offset_s_cmp_ge0000_cy_3_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X36Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_3_IBUF_1317,
      O => Mcompar_offset_s_cmp_ge0000_cy_3_CY0G_3852
    );
  Mcompar_offset_s_cmp_ge0000_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X36Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0000_lut(3),
      O => Mcompar_offset_s_cmp_ge0000_cy_3_CYSELG_3844
    );
  Mcompar_offset_s_cmp_ge0000_lut_3_Q : X_LUT4
    generic map(
      INIT => X"C3C3",
      LOC => "SLICE_X36Y27"
    )
    port map (
      ADR0 => VCC,
      ADR1 => R_i_3_IBUF_1317,
      ADR2 => G_i_3_IBUF_1319,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0000_lut(3)
    );
  Mcompar_offset_s_cmp_ge0000_cy_5_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X36Y28"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0000_cy_5_CY0F_3898,
      IB => Mcompar_offset_s_cmp_ge0000_cy_5_CY0F_3898,
      SEL => Mcompar_offset_s_cmp_ge0000_cy_5_CYSELF_3889,
      O => Mcompar_offset_s_cmp_ge0000_cy_5_CYMUXF2_3884
    );
  Mcompar_offset_s_cmp_ge0000_cy_5_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X36Y28",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_4_IBUF_1292,
      O => Mcompar_offset_s_cmp_ge0000_cy_5_CY0F_3898
    );
  Mcompar_offset_s_cmp_ge0000_cy_5_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X36Y28",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0000_lut(4),
      O => Mcompar_offset_s_cmp_ge0000_cy_5_CYSELF_3889
    );
  Mcompar_offset_s_cmp_ge0000_cy_5_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X36Y28",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0000_cy_3_CYMUXFAST_3857,
      O => Mcompar_offset_s_cmp_ge0000_cy_5_FASTCARRY_3886
    );
  Mcompar_offset_s_cmp_ge0000_cy_5_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X36Y28"
    )
    port map (
      I0 => Mcompar_offset_s_cmp_ge0000_cy_5_CYSELG_3875,
      I1 => Mcompar_offset_s_cmp_ge0000_cy_5_CYSELF_3889,
      O => Mcompar_offset_s_cmp_ge0000_cy_5_CYAND_3887
    );
  Mcompar_offset_s_cmp_ge0000_cy_5_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X36Y28"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0000_cy_5_CYMUXG2_3885,
      IB => Mcompar_offset_s_cmp_ge0000_cy_5_FASTCARRY_3886,
      SEL => Mcompar_offset_s_cmp_ge0000_cy_5_CYAND_3887,
      O => Mcompar_offset_s_cmp_ge0000_cy_5_CYMUXFAST_3888
    );
  Mcompar_offset_s_cmp_ge0000_cy_5_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X36Y28"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0000_cy_5_CY0G_3883,
      IB => Mcompar_offset_s_cmp_ge0000_cy_5_CYMUXF2_3884,
      SEL => Mcompar_offset_s_cmp_ge0000_cy_5_CYSELG_3875,
      O => Mcompar_offset_s_cmp_ge0000_cy_5_CYMUXG2_3885
    );
  Mcompar_offset_s_cmp_ge0000_cy_5_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X36Y28",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_5_IBUF_1313,
      O => Mcompar_offset_s_cmp_ge0000_cy_5_CY0G_3883
    );
  Mcompar_offset_s_cmp_ge0000_cy_5_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X36Y28",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0000_lut(5),
      O => Mcompar_offset_s_cmp_ge0000_cy_5_CYSELG_3875
    );
  Mcompar_offset_s_cmp_ge0000_lut_5_Q : X_LUT4
    generic map(
      INIT => X"A5A5",
      LOC => "SLICE_X36Y28"
    )
    port map (
      ADR0 => R_i_5_IBUF_1313,
      ADR1 => VCC,
      ADR2 => G_i_5_IBUF_1312,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0000_lut(5)
    );
  offset_s_cmp_ge0000_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X36Y29"
    )
    port map (
      IA => offset_s_cmp_ge0000_CY0F_3929,
      IB => offset_s_cmp_ge0000_CY0F_3929,
      SEL => offset_s_cmp_ge0000_CYSELF_3920,
      O => offset_s_cmp_ge0000_CYMUXF2_3915
    );
  offset_s_cmp_ge0000_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X36Y29",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_6_IBUF_1305,
      O => offset_s_cmp_ge0000_CY0F_3929
    );
  offset_s_cmp_ge0000_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X36Y29",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0000_lut(6),
      O => offset_s_cmp_ge0000_CYSELF_3920
    );
  offset_s_cmp_ge0000_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X36Y29",
      PATHPULSE => 757 ps
    )
    port map (
      I => offset_s_cmp_ge0000_CYMUXFAST_3919,
      O => offset_s_cmp_ge0000
    );
  offset_s_cmp_ge0000_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X36Y29",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0000_cy_5_CYMUXFAST_3888,
      O => offset_s_cmp_ge0000_FASTCARRY_3917
    );
  offset_s_cmp_ge0000_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X36Y29"
    )
    port map (
      I0 => offset_s_cmp_ge0000_CYSELG_3906,
      I1 => offset_s_cmp_ge0000_CYSELF_3920,
      O => offset_s_cmp_ge0000_CYAND_3918
    );
  offset_s_cmp_ge0000_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X36Y29"
    )
    port map (
      IA => offset_s_cmp_ge0000_CYMUXG2_3916,
      IB => offset_s_cmp_ge0000_FASTCARRY_3917,
      SEL => offset_s_cmp_ge0000_CYAND_3918,
      O => offset_s_cmp_ge0000_CYMUXFAST_3919
    );
  offset_s_cmp_ge0000_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X36Y29"
    )
    port map (
      IA => offset_s_cmp_ge0000_CY0G_3914,
      IB => offset_s_cmp_ge0000_CYMUXF2_3915,
      SEL => offset_s_cmp_ge0000_CYSELG_3906,
      O => offset_s_cmp_ge0000_CYMUXG2_3916
    );
  offset_s_cmp_ge0000_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X36Y29",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_7_IBUF_1271,
      O => offset_s_cmp_ge0000_CY0G_3914
    );
  offset_s_cmp_ge0000_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X36Y29",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0000_lut(7),
      O => offset_s_cmp_ge0000_CYSELG_3906
    );
  Mcompar_offset_s_cmp_ge0000_lut_7_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X36Y29"
    )
    port map (
      ADR0 => G_i_7_IBUF_1275,
      ADR1 => R_i_7_IBUF_1271,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0000_lut(7)
    );
  Mcompar_min_s_cmp_le0002_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X37Y24"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0002_cy_1_CY0F_3958,
      IB => Mcompar_min_s_cmp_le0002_cy_1_CYINIT_3959,
      SEL => Mcompar_min_s_cmp_le0002_cy_1_CYSELF_3950,
      O => Mcompar_min_s_cmp_le0002_cy(0)
    );
  Mcompar_min_s_cmp_le0002_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X37Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => Mcompar_min_s_cmp_le0002_cy_1_CYINIT_3959
    );
  Mcompar_min_s_cmp_le0002_cy_1_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X37Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_0_IBUF_1301,
      O => Mcompar_min_s_cmp_le0002_cy_1_CY0F_3958
    );
  Mcompar_min_s_cmp_le0002_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0002_lut(0),
      O => Mcompar_min_s_cmp_le0002_cy_1_CYSELF_3950
    );
  Mcompar_min_s_cmp_le0002_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X37Y24"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0002_cy_1_CY0G_3945,
      IB => Mcompar_min_s_cmp_le0002_cy(0),
      SEL => Mcompar_min_s_cmp_le0002_cy_1_CYSELG_3937,
      O => Mcompar_min_s_cmp_le0002_cy_1_CYMUXG_3947
    );
  Mcompar_min_s_cmp_le0002_cy_1_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X37Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_1_IBUF_1288,
      O => Mcompar_min_s_cmp_le0002_cy_1_CY0G_3945
    );
  Mcompar_min_s_cmp_le0002_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0002_lut(1),
      O => Mcompar_min_s_cmp_le0002_cy_1_CYSELG_3937
    );
  Mcompar_min_s_cmp_le0002_lut_1_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X37Y24"
    )
    port map (
      ADR0 => R_i_1_IBUF_1288,
      ADR1 => G_i_1_IBUF_1287,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0002_lut(1)
    );
  Mcompar_min_s_cmp_le0002_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y25"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0002_cy_3_CY0F_3990,
      IB => Mcompar_min_s_cmp_le0002_cy_3_CY0F_3990,
      SEL => Mcompar_min_s_cmp_le0002_cy_3_CYSELF_3981,
      O => Mcompar_min_s_cmp_le0002_cy_3_CYMUXF2_3976
    );
  Mcompar_min_s_cmp_le0002_cy_3_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X37Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_2_IBUF_1280,
      O => Mcompar_min_s_cmp_le0002_cy_3_CY0F_3990
    );
  Mcompar_min_s_cmp_le0002_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0002_lut(2),
      O => Mcompar_min_s_cmp_le0002_cy_3_CYSELF_3981
    );
  Mcompar_min_s_cmp_le0002_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0002_cy_1_CYMUXG_3947,
      O => Mcompar_min_s_cmp_le0002_cy_3_FASTCARRY_3978
    );
  Mcompar_min_s_cmp_le0002_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y25"
    )
    port map (
      I0 => Mcompar_min_s_cmp_le0002_cy_3_CYSELG_3967,
      I1 => Mcompar_min_s_cmp_le0002_cy_3_CYSELF_3981,
      O => Mcompar_min_s_cmp_le0002_cy_3_CYAND_3979
    );
  Mcompar_min_s_cmp_le0002_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y25"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0002_cy_3_CYMUXG2_3977,
      IB => Mcompar_min_s_cmp_le0002_cy_3_FASTCARRY_3978,
      SEL => Mcompar_min_s_cmp_le0002_cy_3_CYAND_3979,
      O => Mcompar_min_s_cmp_le0002_cy_3_CYMUXFAST_3980
    );
  Mcompar_min_s_cmp_le0002_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y25"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0002_cy_3_CY0G_3975,
      IB => Mcompar_min_s_cmp_le0002_cy_3_CYMUXF2_3976,
      SEL => Mcompar_min_s_cmp_le0002_cy_3_CYSELG_3967,
      O => Mcompar_min_s_cmp_le0002_cy_3_CYMUXG2_3977
    );
  Mcompar_min_s_cmp_le0002_cy_3_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X37Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_3_IBUF_1317,
      O => Mcompar_min_s_cmp_le0002_cy_3_CY0G_3975
    );
  Mcompar_min_s_cmp_le0002_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0002_lut(3),
      O => Mcompar_min_s_cmp_le0002_cy_3_CYSELG_3967
    );
  Mcompar_min_s_cmp_le0002_lut_3_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X37Y25"
    )
    port map (
      ADR0 => R_i_3_IBUF_1317,
      ADR1 => G_i_3_IBUF_1319,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0002_lut(3)
    );
  Mcompar_min_s_cmp_le0002_cy_5_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y26"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0002_cy_5_CY0F_4021,
      IB => Mcompar_min_s_cmp_le0002_cy_5_CY0F_4021,
      SEL => Mcompar_min_s_cmp_le0002_cy_5_CYSELF_4012,
      O => Mcompar_min_s_cmp_le0002_cy_5_CYMUXF2_4007
    );
  Mcompar_min_s_cmp_le0002_cy_5_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X37Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_4_IBUF_1292,
      O => Mcompar_min_s_cmp_le0002_cy_5_CY0F_4021
    );
  Mcompar_min_s_cmp_le0002_cy_5_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0002_lut(4),
      O => Mcompar_min_s_cmp_le0002_cy_5_CYSELF_4012
    );
  Mcompar_min_s_cmp_le0002_cy_5_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0002_cy_3_CYMUXFAST_3980,
      O => Mcompar_min_s_cmp_le0002_cy_5_FASTCARRY_4009
    );
  Mcompar_min_s_cmp_le0002_cy_5_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y26"
    )
    port map (
      I0 => Mcompar_min_s_cmp_le0002_cy_5_CYSELG_3998,
      I1 => Mcompar_min_s_cmp_le0002_cy_5_CYSELF_4012,
      O => Mcompar_min_s_cmp_le0002_cy_5_CYAND_4010
    );
  Mcompar_min_s_cmp_le0002_cy_5_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y26"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0002_cy_5_CYMUXG2_4008,
      IB => Mcompar_min_s_cmp_le0002_cy_5_FASTCARRY_4009,
      SEL => Mcompar_min_s_cmp_le0002_cy_5_CYAND_4010,
      O => Mcompar_min_s_cmp_le0002_cy_5_CYMUXFAST_4011
    );
  Mcompar_min_s_cmp_le0002_cy_5_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y26"
    )
    port map (
      IA => Mcompar_min_s_cmp_le0002_cy_5_CY0G_4006,
      IB => Mcompar_min_s_cmp_le0002_cy_5_CYMUXF2_4007,
      SEL => Mcompar_min_s_cmp_le0002_cy_5_CYSELG_3998,
      O => Mcompar_min_s_cmp_le0002_cy_5_CYMUXG2_4008
    );
  Mcompar_min_s_cmp_le0002_cy_5_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X37Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_5_IBUF_1313,
      O => Mcompar_min_s_cmp_le0002_cy_5_CY0G_4006
    );
  Mcompar_min_s_cmp_le0002_cy_5_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y26",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0002_lut(5),
      O => Mcompar_min_s_cmp_le0002_cy_5_CYSELG_3998
    );
  Mcompar_min_s_cmp_le0002_lut_5_Q : X_LUT4
    generic map(
      INIT => X"AA55",
      LOC => "SLICE_X37Y26"
    )
    port map (
      ADR0 => R_i_5_IBUF_1313,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => G_i_5_IBUF_1312,
      O => Mcompar_min_s_cmp_le0002_lut(5)
    );
  min_s_cmp_le0002_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y27"
    )
    port map (
      IA => min_s_cmp_le0002_CY0F_4052,
      IB => min_s_cmp_le0002_CY0F_4052,
      SEL => min_s_cmp_le0002_CYSELF_4043,
      O => min_s_cmp_le0002_CYMUXF2_4038
    );
  min_s_cmp_le0002_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X37Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_6_IBUF_1305,
      O => min_s_cmp_le0002_CY0F_4052
    );
  min_s_cmp_le0002_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X37Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0002_lut(6),
      O => min_s_cmp_le0002_CYSELF_4043
    );
  min_s_cmp_le0002_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X37Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => min_s_cmp_le0002_CYMUXFAST_4042,
      O => min_s_cmp_le0002
    );
  min_s_cmp_le0002_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X37Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0002_cy_5_CYMUXFAST_4011,
      O => min_s_cmp_le0002_FASTCARRY_4040
    );
  min_s_cmp_le0002_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X37Y27"
    )
    port map (
      I0 => min_s_cmp_le0002_CYSELG_4029,
      I1 => min_s_cmp_le0002_CYSELF_4043,
      O => min_s_cmp_le0002_CYAND_4041
    );
  min_s_cmp_le0002_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X37Y27"
    )
    port map (
      IA => min_s_cmp_le0002_CYMUXG2_4039,
      IB => min_s_cmp_le0002_FASTCARRY_4040,
      SEL => min_s_cmp_le0002_CYAND_4041,
      O => min_s_cmp_le0002_CYMUXFAST_4042
    );
  min_s_cmp_le0002_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X37Y27"
    )
    port map (
      IA => min_s_cmp_le0002_CY0G_4037,
      IB => min_s_cmp_le0002_CYMUXF2_4038,
      SEL => min_s_cmp_le0002_CYSELG_4029,
      O => min_s_cmp_le0002_CYMUXG2_4039
    );
  min_s_cmp_le0002_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X37Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_7_IBUF_1271,
      O => min_s_cmp_le0002_CY0G_4037
    );
  min_s_cmp_le0002_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X37Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_min_s_cmp_le0002_lut(7),
      O => min_s_cmp_le0002_CYSELG_4029
    );
  Mcompar_min_s_cmp_le0002_lut_7_Q : X_LUT4
    generic map(
      INIT => X"CC33",
      LOC => "SLICE_X37Y27"
    )
    port map (
      ADR0 => VCC,
      ADR1 => R_i_7_IBUF_1271,
      ADR2 => VCC,
      ADR3 => G_i_7_IBUF_1275,
      O => Mcompar_min_s_cmp_le0002_lut(7)
    );
  Mcompar_offset_s_cmp_ge0002_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X32Y22"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0002_cy_1_CY0F_4081,
      IB => Mcompar_offset_s_cmp_ge0002_cy_1_CYINIT_4082,
      SEL => Mcompar_offset_s_cmp_ge0002_cy_1_CYSELF_4073,
      O => Mcompar_offset_s_cmp_ge0002_cy(0)
    );
  Mcompar_offset_s_cmp_ge0002_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X32Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => Mcompar_offset_s_cmp_ge0002_cy_1_CYINIT_4082
    );
  Mcompar_offset_s_cmp_ge0002_cy_1_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X32Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_0_IBUF_1300,
      O => Mcompar_offset_s_cmp_ge0002_cy_1_CY0F_4081
    );
  Mcompar_offset_s_cmp_ge0002_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X32Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0002_lut(0),
      O => Mcompar_offset_s_cmp_ge0002_cy_1_CYSELF_4073
    );
  Mcompar_offset_s_cmp_ge0002_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X32Y22"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0002_cy_1_CY0G_4068,
      IB => Mcompar_offset_s_cmp_ge0002_cy(0),
      SEL => Mcompar_offset_s_cmp_ge0002_cy_1_CYSELG_4060,
      O => Mcompar_offset_s_cmp_ge0002_cy_1_CYMUXG_4070
    );
  Mcompar_offset_s_cmp_ge0002_cy_1_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X32Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_1_IBUF_1287,
      O => Mcompar_offset_s_cmp_ge0002_cy_1_CY0G_4068
    );
  Mcompar_offset_s_cmp_ge0002_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X32Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0002_lut(1),
      O => Mcompar_offset_s_cmp_ge0002_cy_1_CYSELG_4060
    );
  Mcompar_offset_s_cmp_ge0002_lut_1_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X32Y22"
    )
    port map (
      ADR0 => B_i_1_IBUF_1289,
      ADR1 => G_i_1_IBUF_1287,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0002_lut(1)
    );
  Mcompar_offset_s_cmp_ge0002_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X32Y23"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0002_cy_3_CY0F_4113,
      IB => Mcompar_offset_s_cmp_ge0002_cy_3_CY0F_4113,
      SEL => Mcompar_offset_s_cmp_ge0002_cy_3_CYSELF_4104,
      O => Mcompar_offset_s_cmp_ge0002_cy_3_CYMUXF2_4099
    );
  Mcompar_offset_s_cmp_ge0002_cy_3_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X32Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_2_IBUF_1284,
      O => Mcompar_offset_s_cmp_ge0002_cy_3_CY0F_4113
    );
  Mcompar_offset_s_cmp_ge0002_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X32Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0002_lut(2),
      O => Mcompar_offset_s_cmp_ge0002_cy_3_CYSELF_4104
    );
  Mcompar_offset_s_cmp_ge0002_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X32Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0002_cy_1_CYMUXG_4070,
      O => Mcompar_offset_s_cmp_ge0002_cy_3_FASTCARRY_4101
    );
  Mcompar_offset_s_cmp_ge0002_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X32Y23"
    )
    port map (
      I0 => Mcompar_offset_s_cmp_ge0002_cy_3_CYSELG_4090,
      I1 => Mcompar_offset_s_cmp_ge0002_cy_3_CYSELF_4104,
      O => Mcompar_offset_s_cmp_ge0002_cy_3_CYAND_4102
    );
  Mcompar_offset_s_cmp_ge0002_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X32Y23"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0002_cy_3_CYMUXG2_4100,
      IB => Mcompar_offset_s_cmp_ge0002_cy_3_FASTCARRY_4101,
      SEL => Mcompar_offset_s_cmp_ge0002_cy_3_CYAND_4102,
      O => Mcompar_offset_s_cmp_ge0002_cy_3_CYMUXFAST_4103
    );
  Mcompar_offset_s_cmp_ge0002_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X32Y23"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0002_cy_3_CY0G_4098,
      IB => Mcompar_offset_s_cmp_ge0002_cy_3_CYMUXF2_4099,
      SEL => Mcompar_offset_s_cmp_ge0002_cy_3_CYSELG_4090,
      O => Mcompar_offset_s_cmp_ge0002_cy_3_CYMUXG2_4100
    );
  Mcompar_offset_s_cmp_ge0002_cy_3_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X32Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_3_IBUF_1319,
      O => Mcompar_offset_s_cmp_ge0002_cy_3_CY0G_4098
    );
  Mcompar_offset_s_cmp_ge0002_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X32Y23",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0002_lut(3),
      O => Mcompar_offset_s_cmp_ge0002_cy_3_CYSELG_4090
    );
  Mcompar_offset_s_cmp_ge0002_lut_3_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X32Y23"
    )
    port map (
      ADR0 => G_i_3_IBUF_1319,
      ADR1 => B_i_3_IBUF_1318,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0002_lut(3)
    );
  Mcompar_offset_s_cmp_ge0002_cy_5_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X32Y24"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0002_cy_5_CY0F_4144,
      IB => Mcompar_offset_s_cmp_ge0002_cy_5_CY0F_4144,
      SEL => Mcompar_offset_s_cmp_ge0002_cy_5_CYSELF_4135,
      O => Mcompar_offset_s_cmp_ge0002_cy_5_CYMUXF2_4130
    );
  Mcompar_offset_s_cmp_ge0002_cy_5_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X32Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_4_IBUF_1294,
      O => Mcompar_offset_s_cmp_ge0002_cy_5_CY0F_4144
    );
  Mcompar_offset_s_cmp_ge0002_cy_5_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X32Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0002_lut(4),
      O => Mcompar_offset_s_cmp_ge0002_cy_5_CYSELF_4135
    );
  Mcompar_offset_s_cmp_ge0002_cy_5_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X32Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0002_cy_3_CYMUXFAST_4103,
      O => Mcompar_offset_s_cmp_ge0002_cy_5_FASTCARRY_4132
    );
  Mcompar_offset_s_cmp_ge0002_cy_5_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X32Y24"
    )
    port map (
      I0 => Mcompar_offset_s_cmp_ge0002_cy_5_CYSELG_4121,
      I1 => Mcompar_offset_s_cmp_ge0002_cy_5_CYSELF_4135,
      O => Mcompar_offset_s_cmp_ge0002_cy_5_CYAND_4133
    );
  Mcompar_offset_s_cmp_ge0002_cy_5_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X32Y24"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0002_cy_5_CYMUXG2_4131,
      IB => Mcompar_offset_s_cmp_ge0002_cy_5_FASTCARRY_4132,
      SEL => Mcompar_offset_s_cmp_ge0002_cy_5_CYAND_4133,
      O => Mcompar_offset_s_cmp_ge0002_cy_5_CYMUXFAST_4134
    );
  Mcompar_offset_s_cmp_ge0002_cy_5_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X32Y24"
    )
    port map (
      IA => Mcompar_offset_s_cmp_ge0002_cy_5_CY0G_4129,
      IB => Mcompar_offset_s_cmp_ge0002_cy_5_CYMUXF2_4130,
      SEL => Mcompar_offset_s_cmp_ge0002_cy_5_CYSELG_4121,
      O => Mcompar_offset_s_cmp_ge0002_cy_5_CYMUXG2_4131
    );
  Mcompar_offset_s_cmp_ge0002_cy_5_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X32Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_5_IBUF_1312,
      O => Mcompar_offset_s_cmp_ge0002_cy_5_CY0G_4129
    );
  Mcompar_offset_s_cmp_ge0002_cy_5_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X32Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0002_lut(5),
      O => Mcompar_offset_s_cmp_ge0002_cy_5_CYSELG_4121
    );
  Mcompar_offset_s_cmp_ge0002_lut_5_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X32Y24"
    )
    port map (
      ADR0 => G_i_5_IBUF_1312,
      ADR1 => B_i_5_IBUF_1314,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0002_lut(5)
    );
  offset_s_cmp_ge0002_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X32Y25"
    )
    port map (
      IA => offset_s_cmp_ge0002_CY0F_4175,
      IB => offset_s_cmp_ge0002_CY0F_4175,
      SEL => offset_s_cmp_ge0002_CYSELF_4166,
      O => offset_s_cmp_ge0002_CYMUXF2_4161
    );
  offset_s_cmp_ge0002_CY0F : X_BUF
    generic map(
      LOC => "SLICE_X32Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_6_IBUF_1307,
      O => offset_s_cmp_ge0002_CY0F_4175
    );
  offset_s_cmp_ge0002_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X32Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0002_lut(6),
      O => offset_s_cmp_ge0002_CYSELF_4166
    );
  offset_s_cmp_ge0002_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X32Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => offset_s_cmp_ge0002_CYMUXFAST_4165,
      O => offset_s_cmp_ge0002
    );
  offset_s_cmp_ge0002_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X32Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0002_cy_5_CYMUXFAST_4134,
      O => offset_s_cmp_ge0002_FASTCARRY_4163
    );
  offset_s_cmp_ge0002_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X32Y25"
    )
    port map (
      I0 => offset_s_cmp_ge0002_CYSELG_4152,
      I1 => offset_s_cmp_ge0002_CYSELF_4166,
      O => offset_s_cmp_ge0002_CYAND_4164
    );
  offset_s_cmp_ge0002_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X32Y25"
    )
    port map (
      IA => offset_s_cmp_ge0002_CYMUXG2_4162,
      IB => offset_s_cmp_ge0002_FASTCARRY_4163,
      SEL => offset_s_cmp_ge0002_CYAND_4164,
      O => offset_s_cmp_ge0002_CYMUXFAST_4165
    );
  offset_s_cmp_ge0002_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X32Y25"
    )
    port map (
      IA => offset_s_cmp_ge0002_CY0G_4160,
      IB => offset_s_cmp_ge0002_CYMUXF2_4161,
      SEL => offset_s_cmp_ge0002_CYSELG_4152,
      O => offset_s_cmp_ge0002_CYMUXG2_4162
    );
  offset_s_cmp_ge0002_CY0G : X_BUF
    generic map(
      LOC => "SLICE_X32Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_7_IBUF_1275,
      O => offset_s_cmp_ge0002_CY0G_4160
    );
  offset_s_cmp_ge0002_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X32Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => Mcompar_offset_s_cmp_ge0002_lut(7),
      O => offset_s_cmp_ge0002_CYSELG_4152
    );
  Mcompar_offset_s_cmp_ge0002_lut_7_Q : X_LUT4
    generic map(
      INIT => X"C3C3",
      LOC => "SLICE_X32Y25"
    )
    port map (
      ADR0 => VCC,
      ADR1 => G_i_7_IBUF_1275,
      ADR2 => B_i_7_IBUF_1273,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0002_lut(7)
    );
  Y_o_1_OBUF : X_OBUF
    generic map(
      LOC => "PAD22"
    )
    port map (
      I => Y_o_1_O,
      O => Y_o(1)
    );
  Y_o_2_OBUF : X_OBUF
    generic map(
      LOC => "PAD76"
    )
    port map (
      I => Y_o_2_O,
      O => Y_o(2)
    );
  Y_o_3_OBUF : X_OBUF
    generic map(
      LOC => "PAD67"
    )
    port map (
      I => Y_o_3_O,
      O => Y_o(3)
    );
  Y_o_4_OBUF : X_OBUF
    generic map(
      LOC => "PAD74"
    )
    port map (
      I => Y_o_4_O,
      O => Y_o(4)
    );
  Y_o_5_OBUF : X_OBUF
    generic map(
      LOC => "PAD68"
    )
    port map (
      I => Y_o_5_O,
      O => Y_o(5)
    );
  Y_o_6_OBUF : X_OBUF
    generic map(
      LOC => "PAD73"
    )
    port map (
      I => Y_o_6_O,
      O => Y_o(6)
    );
  Y_o_7_OBUF : X_OBUF
    generic map(
      LOC => "PAD66"
    )
    port map (
      I => Y_o_7_O,
      O => Y_o(7)
    );
  B_i_0_IBUF : X_BUF
    generic map(
      LOC => "PAD63",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i(0),
      O => B_i_0_INBUF
    );
  B_i_0_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD63",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_0_INBUF,
      O => B_i_0_IBUF_1326
    );
  B_i_1_IBUF : X_BUF
    generic map(
      LOC => "PAD65",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i(1),
      O => B_i_1_INBUF
    );
  B_i_1_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD65",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_1_INBUF,
      O => B_i_1_IBUF_1289
    );
  B_i_2_IBUF : X_BUF
    generic map(
      LOC => "PAD60",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i(2),
      O => B_i_2_INBUF
    );
  B_i_2_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD60",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_2_INBUF,
      O => B_i_2_IBUF_1282
    );
  B_i_3_IBUF : X_BUF
    generic map(
      LOC => "PAD59",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i(3),
      O => B_i_3_INBUF
    );
  B_i_3_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD59",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_3_INBUF,
      O => B_i_3_IBUF_1318
    );
  R_i_0_IBUF : X_BUF
    generic map(
      LOC => "PAD75",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i(0),
      O => R_i_0_INBUF
    );
  R_i_0_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD75",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_0_INBUF,
      O => R_i_0_IBUF_1301
    );
  B_i_4_IBUF : X_BUF
    generic map(
      LOC => "PAD89",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i(4),
      O => B_i_4_INBUF
    );
  B_i_4_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD89",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_4_INBUF,
      O => B_i_4_IBUF_1293
    );
  R_i_1_IBUF : X_BUF
    generic map(
      LOC => "PAD86",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i(1),
      O => R_i_1_INBUF
    );
  R_i_1_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD86",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_1_INBUF,
      O => R_i_1_IBUF_1288
    );
  B_i_5_IBUF : X_BUF
    generic map(
      LOC => "PAD97",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i(5),
      O => B_i_5_INBUF
    );
  B_i_5_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD97",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_5_INBUF,
      O => B_i_5_IBUF_1314
    );
  R_i_2_IBUF : X_BUF
    generic map(
      LOC => "PAD61",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i(2),
      O => R_i_2_INBUF
    );
  R_i_2_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD61",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_2_INBUF,
      O => R_i_2_IBUF_1280
    );
  B_i_6_IBUF : X_BUF
    generic map(
      LOC => "PAD91",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i(6),
      O => B_i_6_INBUF
    );
  B_i_6_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD91",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_6_INBUF,
      O => B_i_6_IBUF_1306
    );
  R_i_3_IBUF : X_BUF
    generic map(
      LOC => "PAD82",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i(3),
      O => R_i_3_INBUF
    );
  R_i_3_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD82",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_3_INBUF,
      O => R_i_3_IBUF_1317
    );
  B_i_7_IBUF : X_BUF
    generic map(
      LOC => "PAD62",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i(7),
      O => B_i_7_INBUF
    );
  B_i_7_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD62",
      PATHPULSE => 757 ps
    )
    port map (
      I => B_i_7_INBUF,
      O => B_i_7_IBUF_1273
    );
  R_i_4_IBUF : X_BUF
    generic map(
      LOC => "PAD64",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i(4),
      O => R_i_4_INBUF
    );
  R_i_4_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD64",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_4_INBUF,
      O => R_i_4_IBUF_1292
    );
  R_i_5_IBUF : X_BUF
    generic map(
      LOC => "PAD52",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i(5),
      O => R_i_5_INBUF
    );
  R_i_5_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD52",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_5_INBUF,
      O => R_i_5_IBUF_1313
    );
  clk_i_BUFGP_IBUFG : X_BUF
    generic map(
      LOC => "PAD123",
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_i,
      O => clk_i_INBUF
    );
  R_i_6_IBUF : X_BUF
    generic map(
      LOC => "PAD51",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i(6),
      O => R_i_6_INBUF
    );
  R_i_6_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD51",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_6_INBUF,
      O => R_i_6_IBUF_1305
    );
  R_i_7_IBUF : X_BUF
    generic map(
      LOC => "PAD50",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i(7),
      O => R_i_7_INBUF
    );
  R_i_7_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD50",
      PATHPULSE => 757 ps
    )
    port map (
      I => R_i_7_INBUF,
      O => R_i_7_IBUF_1271
    );
  H_o_0_OBUF : X_OBUF
    generic map(
      LOC => "PAD20"
    )
    port map (
      I => H_o_0_O,
      O => H_o(0)
    );
  H_o_1_OBUF : X_OBUF
    generic map(
      LOC => "PAD182"
    )
    port map (
      I => H_o_1_O,
      O => H_o(1)
    );
  H_o_2_OBUF : X_OBUF
    generic map(
      LOC => "PAD174"
    )
    port map (
      I => H_o_2_O,
      O => H_o(2)
    );
  H_o_3_OBUF : X_OBUF
    generic map(
      LOC => "PAD187"
    )
    port map (
      I => H_o_3_O,
      O => H_o(3)
    );
  H_o_4_OBUF : X_OBUF
    generic map(
      LOC => "PAD185"
    )
    port map (
      I => H_o_4_O,
      O => H_o(4)
    );
  H_o_5_OBUF : X_OBUF
    generic map(
      LOC => "PAD13"
    )
    port map (
      I => H_o_5_O,
      O => H_o(5)
    );
  H_o_6_OBUF : X_OBUF
    generic map(
      LOC => "PAD23"
    )
    port map (
      I => H_o_6_O,
      O => H_o(6)
    );
  H_o_7_OBUF : X_OBUF
    generic map(
      LOC => "PAD179"
    )
    port map (
      I => H_o_7_O,
      O => H_o(7)
    );
  G_i_0_IBUF : X_BUF
    generic map(
      LOC => "PAD87",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i(0),
      O => G_i_0_INBUF
    );
  G_i_0_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD87",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_0_INBUF,
      O => G_i_0_IBUF_1300
    );
  G_i_1_IBUF : X_BUF
    generic map(
      LOC => "PAD88",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i(1),
      O => G_i_1_INBUF
    );
  G_i_1_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD88",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_1_INBUF,
      O => G_i_1_IBUF_1287
    );
  G_i_2_IBUF : X_BUF
    generic map(
      LOC => "PAD85",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i(2),
      O => G_i_2_INBUF
    );
  G_i_2_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD85",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_2_INBUF,
      O => G_i_2_IBUF_1284
    );
  G_i_3_IBUF : X_BUF
    generic map(
      LOC => "PAD84",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i(3),
      O => G_i_3_INBUF
    );
  G_i_3_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD84",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_3_INBUF,
      O => G_i_3_IBUF_1319
    );
  G_i_4_IBUF : X_BUF
    generic map(
      LOC => "PAD83",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i(4),
      O => G_i_4_INBUF
    );
  G_i_4_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD83",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_4_INBUF,
      O => G_i_4_IBUF_1294
    );
  G_i_5_IBUF : X_BUF
    generic map(
      LOC => "PAD90",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i(5),
      O => G_i_5_INBUF
    );
  G_i_5_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD90",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_5_INBUF,
      O => G_i_5_IBUF_1312
    );
  G_i_6_IBUF : X_BUF
    generic map(
      LOC => "PAD81",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i(6),
      O => G_i_6_INBUF
    );
  G_i_6_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD81",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_6_INBUF,
      O => G_i_6_IBUF_1307
    );
  G_i_7_IBUF : X_BUF
    generic map(
      LOC => "PAD98",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i(7),
      O => G_i_7_INBUF
    );
  G_i_7_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD98",
      PATHPULSE => 757 ps
    )
    port map (
      I => G_i_7_INBUF,
      O => G_i_7_IBUF_1275
    );
  Y_o_0_OBUF : X_OBUF
    generic map(
      LOC => "PAD171"
    )
    port map (
      I => Y_o_0_O,
      O => Y_o(0)
    );
  clk_i_BUFGP_BUFG : X_BUFGMUX
    generic map(
      LOC => "BUFGMUX0"
    )
    port map (
      I0 => clk_i_BUFGP_BUFG_I0_INV,
      I1 => GND,
      S => clk_i_BUFGP_BUFG_S_INVNOT,
      O => clk_i_BUFGP
    );
  clk_i_BUFGP_BUFG_SINV : X_INV
    generic map(
      LOC => "BUFGMUX0",
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => clk_i_BUFGP_BUFG_S_INVNOT
    );
  clk_i_BUFGP_BUFG_I0_USED : X_BUF
    generic map(
      LOC => "BUFGMUX0",
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_i_INBUF,
      O => clk_i_BUFGP_BUFG_I0_INV
    );
  Mmult_G_output_s : X_MULT18X18
    generic map(
      LOC => "MULT18X18_X1Y2"
    )
    port map (
      A(17) => GLOBAL_LOGIC0,
      A(16) => GLOBAL_LOGIC0,
      A(15) => GLOBAL_LOGIC0,
      A(14) => GLOBAL_LOGIC0,
      A(13) => GLOBAL_LOGIC0,
      A(12) => GLOBAL_LOGIC0,
      A(11) => GLOBAL_LOGIC0,
      A(10) => GLOBAL_LOGIC0,
      A(9) => GLOBAL_LOGIC0,
      A(8) => GLOBAL_LOGIC0,
      A(7) => G_i_7_IBUF_1275,
      A(6) => G_i_6_IBUF_1307,
      A(5) => G_i_5_IBUF_1312,
      A(4) => G_i_4_IBUF_1294,
      A(3) => G_i_3_IBUF_1319,
      A(2) => G_i_2_IBUF_1284,
      A(1) => G_i_1_IBUF_1287,
      A(0) => G_i_0_IBUF_1300,
      B(17) => GLOBAL_LOGIC0,
      B(16) => GLOBAL_LOGIC0,
      B(15) => GLOBAL_LOGIC0,
      B(14) => GLOBAL_LOGIC0,
      B(13) => GLOBAL_LOGIC0,
      B(12) => GLOBAL_LOGIC0,
      B(11) => GLOBAL_LOGIC0,
      B(10) => GLOBAL_LOGIC0,
      B(9) => GLOBAL_LOGIC0,
      B(8) => GLOBAL_LOGIC1,
      B(7) => GLOBAL_LOGIC0,
      B(6) => GLOBAL_LOGIC0,
      B(5) => GLOBAL_LOGIC1,
      B(4) => GLOBAL_LOGIC0,
      B(3) => GLOBAL_LOGIC1,
      B(2) => GLOBAL_LOGIC1,
      B(1) => GLOBAL_LOGIC0,
      B(0) => GLOBAL_LOGIC1,
      P(35) => Mmult_G_output_s_PROD35,
      P(34) => Mmult_G_output_s_PROD34,
      P(33) => Mmult_G_output_s_PROD33,
      P(32) => Mmult_G_output_s_PROD32,
      P(31) => Mmult_G_output_s_PROD31,
      P(30) => Mmult_G_output_s_PROD30,
      P(29) => Mmult_G_output_s_PROD29,
      P(28) => Mmult_G_output_s_PROD28,
      P(27) => Mmult_G_output_s_PROD27,
      P(26) => Mmult_G_output_s_PROD26,
      P(25) => Mmult_G_output_s_PROD25,
      P(24) => Mmult_G_output_s_PROD24,
      P(23) => Mmult_G_output_s_PROD23,
      P(22) => Mmult_G_output_s_PROD22,
      P(21) => Mmult_G_output_s_PROD21,
      P(20) => Mmult_G_output_s_PROD20,
      P(19) => Mmult_G_output_s_PROD19,
      P(18) => Mmult_G_output_s_PROD18,
      P(17) => Mmult_G_output_s_PROD17,
      P(16) => G_output_s(16),
      P(15) => G_output_s(15),
      P(14) => G_output_s(14),
      P(13) => G_output_s(13),
      P(12) => G_output_s(12),
      P(11) => G_output_s(11),
      P(10) => G_output_s(10),
      P(9) => G_output_s(9),
      P(8) => G_output_s(8),
      P(7) => G_output_s(7),
      P(6) => G_output_s(6),
      P(5) => G_output_s(5),
      P(4) => G_output_s(4),
      P(3) => G_output_s(3),
      P(2) => G_output_s(2),
      P(1) => G_output_s(1),
      P(0) => G_output_s(0)
    );
  Mmult_H_large_s : X_MULT18X18
    generic map(
      LOC => "MULT18X18_X0Y2"
    )
    port map (
      A(17) => GLOBAL_LOGIC0,
      A(16) => GLOBAL_LOGIC0,
      A(15) => RAM_out_s(15),
      A(14) => RAM_out_s(14),
      A(13) => RAM_out_s(13),
      A(12) => RAM_out_s(12),
      A(11) => RAM_out_s(11),
      A(10) => RAM_out_s(10),
      A(9) => RAM_out_s(9),
      A(8) => RAM_out_s(8),
      A(7) => RAM_out_s(7),
      A(6) => RAM_out_s(6),
      A(5) => RAM_out_s(5),
      A(4) => RAM_out_s(4),
      A(3) => RAM_out_s(3),
      A(2) => RAM_out_s(2),
      A(1) => RAM_out_s(1),
      A(0) => RAM_out_s(0),
      B(17) => diff_nominat_s(8),
      B(16) => diff_nominat_s(8),
      B(15) => diff_nominat_s(8),
      B(14) => diff_nominat_s(8),
      B(13) => diff_nominat_s(8),
      B(12) => diff_nominat_s(8),
      B(11) => diff_nominat_s(8),
      B(10) => diff_nominat_s(8),
      B(9) => diff_nominat_s(8),
      B(8) => diff_nominat_s(8),
      B(7) => diff_nominat_s(7),
      B(6) => diff_nominat_s(6),
      B(5) => diff_nominat_s(5),
      B(4) => diff_nominat_s(4),
      B(3) => diff_nominat_s(3),
      B(2) => diff_nominat_s(2),
      B(1) => diff_nominat_s(1),
      B(0) => diff_nominat_s(0),
      P(35) => Mmult_H_large_s_PROD35,
      P(34) => Mmult_H_large_s_PROD34,
      P(33) => Mmult_H_large_s_PROD33,
      P(32) => Mmult_H_large_s_PROD32,
      P(31) => Mmult_H_large_s_PROD31,
      P(30) => Mmult_H_large_s_PROD30,
      P(29) => Mmult_H_large_s_PROD29,
      P(28) => Mmult_H_large_s_PROD28,
      P(27) => Mmult_H_large_s_PROD27,
      P(26) => Mmult_H_large_s_PROD26,
      P(25) => Mmult_H_large_s_PROD25,
      P(24) => Mmult_H_large_s_PROD24,
      P(23) => Mmult_H_large_s_PROD23,
      P(22) => Mmult_H_large_s_PROD22,
      P(21) => Mmult_H_large_s_PROD21,
      P(20) => Mmult_H_large_s_PROD20,
      P(19) => Mmult_H_large_s_PROD19,
      P(18) => Mmult_H_large_s_PROD18,
      P(17) => Mmult_H_large_s_PROD17,
      P(16) => H_large_s(16),
      P(15) => H_large_s(15),
      P(14) => H_large_s(14),
      P(13) => H_large_s(13),
      P(12) => H_large_s(12),
      P(11) => H_large_s(11),
      P(10) => H_large_s(10),
      P(9) => H_large_s(9),
      P(8) => Mmult_H_large_s_PROD8,
      P(7) => Mmult_H_large_s_PROD7,
      P(6) => Mmult_H_large_s_PROD6,
      P(5) => Mmult_H_large_s_PROD5,
      P(4) => Mmult_H_large_s_PROD4,
      P(3) => Mmult_H_large_s_PROD3,
      P(2) => Mmult_H_large_s_PROD2,
      P(1) => Mmult_H_large_s_PROD1,
      P(0) => Mmult_H_large_s_PROD0
    );
  Mmult_B_output_s : X_MULT18X18
    generic map(
      LOC => "MULT18X18_X1Y4"
    )
    port map (
      A(17) => GLOBAL_LOGIC0,
      A(16) => GLOBAL_LOGIC0,
      A(15) => GLOBAL_LOGIC0,
      A(14) => GLOBAL_LOGIC0,
      A(13) => GLOBAL_LOGIC0,
      A(12) => GLOBAL_LOGIC0,
      A(11) => GLOBAL_LOGIC0,
      A(10) => GLOBAL_LOGIC0,
      A(9) => GLOBAL_LOGIC0,
      A(8) => GLOBAL_LOGIC0,
      A(7) => B_i_7_IBUF_1273,
      A(6) => B_i_6_IBUF_1306,
      A(5) => B_i_5_IBUF_1314,
      A(4) => B_i_4_IBUF_1293,
      A(3) => B_i_3_IBUF_1318,
      A(2) => B_i_2_IBUF_1282,
      A(1) => B_i_1_IBUF_1289,
      A(0) => B_i_0_IBUF_1326,
      B(17) => GLOBAL_LOGIC0,
      B(16) => GLOBAL_LOGIC0,
      B(15) => GLOBAL_LOGIC0,
      B(14) => GLOBAL_LOGIC0,
      B(13) => GLOBAL_LOGIC0,
      B(12) => GLOBAL_LOGIC0,
      B(11) => GLOBAL_LOGIC0,
      B(10) => GLOBAL_LOGIC0,
      B(9) => GLOBAL_LOGIC0,
      B(8) => GLOBAL_LOGIC0,
      B(7) => GLOBAL_LOGIC0,
      B(6) => GLOBAL_LOGIC0,
      B(5) => GLOBAL_LOGIC1,
      B(4) => GLOBAL_LOGIC1,
      B(3) => GLOBAL_LOGIC1,
      B(2) => GLOBAL_LOGIC0,
      B(1) => GLOBAL_LOGIC1,
      B(0) => GLOBAL_LOGIC0,
      P(35) => Mmult_B_output_s_PROD35,
      P(34) => Mmult_B_output_s_PROD34,
      P(33) => Mmult_B_output_s_PROD33,
      P(32) => Mmult_B_output_s_PROD32,
      P(31) => Mmult_B_output_s_PROD31,
      P(30) => Mmult_B_output_s_PROD30,
      P(29) => Mmult_B_output_s_PROD29,
      P(28) => Mmult_B_output_s_PROD28,
      P(27) => Mmult_B_output_s_PROD27,
      P(26) => Mmult_B_output_s_PROD26,
      P(25) => Mmult_B_output_s_PROD25,
      P(24) => Mmult_B_output_s_PROD24,
      P(23) => Mmult_B_output_s_PROD23,
      P(22) => Mmult_B_output_s_PROD22,
      P(21) => Mmult_B_output_s_PROD21,
      P(20) => Mmult_B_output_s_PROD20,
      P(19) => Mmult_B_output_s_PROD19,
      P(18) => Mmult_B_output_s_PROD18,
      P(17) => Mmult_B_output_s_PROD17,
      P(16) => Mmult_B_output_s_PROD16,
      P(15) => Mmult_B_output_s_PROD15,
      P(14) => B_output_s(14),
      P(13) => B_output_s(13),
      P(12) => B_output_s(12),
      P(11) => B_output_s(11),
      P(10) => B_output_s(10),
      P(9) => B_output_s(9),
      P(8) => B_output_s(8),
      P(7) => B_output_s(7),
      P(6) => B_output_s(6),
      P(5) => B_output_s(5),
      P(4) => B_output_s(4),
      P(3) => B_output_s(3),
      P(2) => B_output_s(2),
      P(1) => B_output_s(1),
      P(0) => B_output_s(0)
    );
  Mmult_R_output_s : X_MULT18X18
    generic map(
      LOC => "MULT18X18_X1Y3"
    )
    port map (
      A(17) => GLOBAL_LOGIC0,
      A(16) => GLOBAL_LOGIC0,
      A(15) => GLOBAL_LOGIC0,
      A(14) => GLOBAL_LOGIC0,
      A(13) => GLOBAL_LOGIC0,
      A(12) => GLOBAL_LOGIC0,
      A(11) => GLOBAL_LOGIC0,
      A(10) => GLOBAL_LOGIC0,
      A(9) => GLOBAL_LOGIC0,
      A(8) => GLOBAL_LOGIC0,
      A(7) => R_i_7_IBUF_1271,
      A(6) => R_i_6_IBUF_1305,
      A(5) => R_i_5_IBUF_1313,
      A(4) => R_i_4_IBUF_1292,
      A(3) => R_i_3_IBUF_1317,
      A(2) => R_i_2_IBUF_1280,
      A(1) => R_i_1_IBUF_1288,
      A(0) => R_i_0_IBUF_1301,
      B(17) => GLOBAL_LOGIC0,
      B(16) => GLOBAL_LOGIC0,
      B(15) => GLOBAL_LOGIC0,
      B(14) => GLOBAL_LOGIC0,
      B(13) => GLOBAL_LOGIC0,
      B(12) => GLOBAL_LOGIC0,
      B(11) => GLOBAL_LOGIC0,
      B(10) => GLOBAL_LOGIC0,
      B(9) => GLOBAL_LOGIC0,
      B(8) => GLOBAL_LOGIC0,
      B(7) => GLOBAL_LOGIC1,
      B(6) => GLOBAL_LOGIC0,
      B(5) => GLOBAL_LOGIC0,
      B(4) => GLOBAL_LOGIC1,
      B(3) => GLOBAL_LOGIC1,
      B(2) => GLOBAL_LOGIC0,
      B(1) => GLOBAL_LOGIC0,
      B(0) => GLOBAL_LOGIC1,
      P(35) => Mmult_R_output_s_PROD35,
      P(34) => Mmult_R_output_s_PROD34,
      P(33) => Mmult_R_output_s_PROD33,
      P(32) => Mmult_R_output_s_PROD32,
      P(31) => Mmult_R_output_s_PROD31,
      P(30) => Mmult_R_output_s_PROD30,
      P(29) => Mmult_R_output_s_PROD29,
      P(28) => Mmult_R_output_s_PROD28,
      P(27) => Mmult_R_output_s_PROD27,
      P(26) => Mmult_R_output_s_PROD26,
      P(25) => Mmult_R_output_s_PROD25,
      P(24) => Mmult_R_output_s_PROD24,
      P(23) => Mmult_R_output_s_PROD23,
      P(22) => Mmult_R_output_s_PROD22,
      P(21) => Mmult_R_output_s_PROD21,
      P(20) => Mmult_R_output_s_PROD20,
      P(19) => Mmult_R_output_s_PROD19,
      P(18) => Mmult_R_output_s_PROD18,
      P(17) => Mmult_R_output_s_PROD17,
      P(16) => R_output_s(16),
      P(15) => R_output_s(15),
      P(14) => R_output_s(14),
      P(13) => R_output_s(13),
      P(12) => R_output_s(12),
      P(11) => R_output_s(11),
      P(10) => R_output_s(10),
      P(9) => R_output_s(9),
      P(8) => R_output_s(8),
      P(7) => R_output_s(7),
      P(6) => R_output_s(6),
      P(5) => R_output_s(5),
      P(4) => R_output_s(4),
      P(3) => R_output_s(3),
      P(2) => R_output_s(2),
      P(1) => R_output_s(1),
      P(0) => R_output_s(0)
    );
  RAMB16_S18_inst : X_RAMB16_S18
    generic map(
      INIT_00 => X"0001AAAA555538E32AAA22221C711861155512F611110F830E380D200C300B60",
      INIT_01 => X"0AAA0A0A097B08FB0888082007C1076B071C06D306900652061805E205B00581",
      INIT_02 => X"0555052B050504E004BD049C047D046004440429041003F803E003CA03B503A1",
      INIT_03 => X"038E037B03690358034803380329031A030C02FE02F102E402D802CC02C002B5",
      INIT_04 => X"02AA02A00295028C0282027902700267025E0256024E0246023E023702300229",
      INIT_05 => X"0222021B0214020E0208020201FC01F601F001EA01E501E001DA01D501D001CB",
      INIT_06 => X"01C701C201BD01B901B401B001AC01A801A401A0019C019801940190018D0189",
      INIT_07 => X"01860182017F017B017801750172016F016C0169016601630160015D015A0158",
      INIT_08 => X"015501520150014D014A0148014601430141013E013C013A0138013501330131",
      INIT_09 => X"012F012D012B01290127012501230121011F011D011B01190118011601140112",
      INIT_0A => X"0111010F010D010C010A01080107010501040102010100FF00FE00FC00FB00F9",
      INIT_0B => X"00F800F600F500F400F200F100F000EE00ED00EC00EA00E900E800E700E500E4",
      INIT_0C => X"00E300E200E100E000DE00DD00DC00DB00DA00D900D800D700D600D500D400D3",
      INIT_0D => X"00D200D100D000CF00CE00CD00CC00CB00CA00C900C800C700C600C500C400C3",
      INIT_0E => X"00C300C200C100C000BF00BE00BD00BD00BC00BB00BA00B900B900B800B700B6",
      INIT_0F => X"00B600B500B400B300B300B200B100B000B000AF00AE00AE00AD00AC00AC00AB",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      SRVAL => X"00000",
      INIT => X"00000",
      WRITE_MODE => "WRITE_FIRST",
      LOC => "RAMB16_X0Y2"
    )
    port map (
      CLK => clk_i_BUFGP,
      EN => GLOBAL_LOGIC1,
      SSR => GLOBAL_LOGIC0,
      WE => GLOBAL_LOGIC0,
      ADDR(9) => GLOBAL_LOGIC0,
      ADDR(8) => GLOBAL_LOGIC0,
      ADDR(7) => diff_min_max_s(7),
      ADDR(6) => diff_min_max_s(6),
      ADDR(5) => diff_min_max_s(5),
      ADDR(4) => diff_min_max_s(4),
      ADDR(3) => diff_min_max_s(3),
      ADDR(2) => diff_min_max_s(2),
      ADDR(1) => diff_min_max_s(1),
      ADDR(0) => diff_min_max_s(0),
      DI(15) => RAMB16_S18_inst_DIA15,
      DI(14) => RAMB16_S18_inst_DIA14,
      DI(13) => RAMB16_S18_inst_DIA13,
      DI(12) => RAMB16_S18_inst_DIA12,
      DI(11) => RAMB16_S18_inst_DIA11,
      DI(10) => RAMB16_S18_inst_DIA10,
      DI(9) => RAMB16_S18_inst_DIA9,
      DI(8) => RAMB16_S18_inst_DIA8,
      DI(7) => RAMB16_S18_inst_DIA7,
      DI(6) => RAMB16_S18_inst_DIA6,
      DI(5) => RAMB16_S18_inst_DIA5,
      DI(4) => RAMB16_S18_inst_DIA4,
      DI(3) => RAMB16_S18_inst_DIA3,
      DI(2) => RAMB16_S18_inst_DIA2,
      DI(1) => RAMB16_S18_inst_DIA1,
      DI(0) => RAMB16_S18_inst_DIA0,
      DIP(1) => RAMB16_S18_inst_DIPA1,
      DIP(0) => RAMB16_S18_inst_DIPA0,
      DO(15) => RAM_out_s(15),
      DO(14) => RAM_out_s(14),
      DO(13) => RAM_out_s(13),
      DO(12) => RAM_out_s(12),
      DO(11) => RAM_out_s(11),
      DO(10) => RAM_out_s(10),
      DO(9) => RAM_out_s(9),
      DO(8) => RAM_out_s(8),
      DO(7) => RAM_out_s(7),
      DO(6) => RAM_out_s(6),
      DO(5) => RAM_out_s(5),
      DO(4) => RAM_out_s(4),
      DO(3) => RAM_out_s(3),
      DO(2) => RAM_out_s(2),
      DO(1) => RAM_out_s(1),
      DO(0) => RAM_out_s(0),
      DOP(1) => RAMB16_S18_inst_DOPA1,
      DOP(0) => RAMB16_S18_inst_DOPA0
    );
  N25_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => N25,
      O => N25_0
    );
  diff_nominat_s_mux0001_6_SW0 : X_LUT4
    generic map(
      INIT => X"E4CC",
      LOC => "SLICE_X28Y22"
    )
    port map (
      ADR0 => offset_s_cmp_ge0003,
      ADR1 => G_i_6_IBUF_1307,
      ADR2 => R_i_6_IBUF_1305,
      ADR3 => offset_s_cmp_ge0002,
      O => N25
    );
  diff_nominat_s_mux0000_7_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_mux0000(7),
      O => diff_nominat_s_mux0000_7_0
    );
  diff_nominat_s_mux0000_7_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y25",
      PATHPULSE => 757 ps
    )
    port map (
      I => N85_pack_1,
      O => N85
    );
  diff_nominat_s_mux0000_7_SW1 : X_LUT4
    generic map(
      INIT => X"E2AA",
      LOC => "SLICE_X24Y25"
    )
    port map (
      ADR0 => R_i_7_IBUF_1271,
      ADR1 => offset_s_cmp_ge0003,
      ADR2 => B_i_7_IBUF_1273,
      ADR3 => offset_s_cmp_ge0002,
      O => N85_pack_1
    );
  max_s_5_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => max_s(5),
      O => max_s_5_0
    );
  max_s_5_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => N73_pack_1,
      O => N73
    );
  max_s_5_SW1 : X_LUT4
    generic map(
      INIT => X"470F",
      LOC => "SLICE_X24Y24"
    )
    port map (
      ADR0 => G_i_5_IBUF_1312,
      ADR1 => offset_s_cmp_ge0003,
      ADR2 => B_i_5_IBUF_1314,
      ADR3 => offset_s_cmp_ge0002,
      O => N73_pack_1
    );
  diff_nominat_s_mux0000_4_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_mux0000(4),
      O => diff_nominat_s_mux0000_4_0
    );
  diff_nominat_s_mux0000_4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y22",
      PATHPULSE => 757 ps
    )
    port map (
      I => N91_pack_1,
      O => N91
    );
  diff_nominat_s_mux0000_4_SW1 : X_LUT4
    generic map(
      INIT => X"BF80",
      LOC => "SLICE_X23Y22"
    )
    port map (
      ADR0 => B_i_4_IBUF_1293,
      ADR1 => offset_s_cmp_ge0003,
      ADR2 => offset_s_cmp_ge0002,
      ADR3 => R_i_4_IBUF_1292,
      O => N91_pack_1
    );
  Msub_diff_min_max_s_lut_7_Q : X_LUT4
    generic map(
      INIT => X"A959",
      LOC => "SLICE_X27Y25"
    )
    port map (
      ADR0 => min_s_7_0,
      ADR1 => R_i_7_IBUF_1271,
      ADR2 => offset_s_0_0,
      ADR3 => N7_0,
      O => Msub_diff_min_max_s_lut(7)
    );
  Madd_H_bias_s_Madd_lut_7_Q : X_LUT4
    generic map(
      INIT => X"9C3C",
      LOC => "SLICE_X6Y25"
    )
    port map (
      ADR0 => offset_s_cmp_ge0003,
      ADR1 => H_large_s(16),
      ADR2 => offset_s_0_0,
      ADR3 => offset_s_cmp_ge0002,
      O => Madd_H_bias_s_Madd_lut(7)
    );
  Madd_H_bias_s_Madd_lut_6_Q : X_LUT4
    generic map(
      INIT => X"6AAA",
      LOC => "SLICE_X6Y25"
    )
    port map (
      ADR0 => H_large_s(15),
      ADR1 => offset_s_cmp_ge0003,
      ADR2 => offset_s_0_0,
      ADR3 => offset_s_cmp_ge0002,
      O => Madd_H_bias_s_Madd_lut(6)
    );
  Mcompar_min_s_cmp_le0000_lut_0_Q : X_LUT4
    generic map(
      INIT => X"CC33",
      LOC => "SLICE_X38Y24"
    )
    port map (
      ADR0 => VCC,
      ADR1 => G_i_0_IBUF_1300,
      ADR2 => VCC,
      ADR3 => R_i_0_IBUF_1301,
      O => Mcompar_min_s_cmp_le0000_lut(0)
    );
  Mcompar_min_s_cmp_le0000_lut_2_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X38Y25"
    )
    port map (
      ADR0 => G_i_2_IBUF_1284,
      ADR1 => R_i_2_IBUF_1280,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0000_lut(2)
    );
  Mcompar_min_s_cmp_le0000_lut_4_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X38Y26"
    )
    port map (
      ADR0 => R_i_4_IBUF_1292,
      ADR1 => G_i_4_IBUF_1294,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0000_lut(4)
    );
  max_s_7_SW0 : X_LUT4
    generic map(
      INIT => X"EA2A",
      LOC => "SLICE_X24Y23"
    )
    port map (
      ADR0 => B_i_7_IBUF_1273,
      ADR1 => offset_s_cmp_ge0002,
      ADR2 => offset_s_cmp_ge0003,
      ADR3 => G_i_7_IBUF_1275,
      O => N7
    );
  diff_nominat_s_mux0001_0_SW0 : X_LUT4
    generic map(
      INIT => X"CAAA",
      LOC => "SLICE_X23Y23"
    )
    port map (
      ADR0 => G_i_0_IBUF_1300,
      ADR1 => R_i_0_IBUF_1301,
      ADR2 => offset_s_cmp_ge0003,
      ADR3 => offset_s_cmp_ge0002,
      O => N37
    );
  max_s_6_Q : X_LUT4
    generic map(
      INIT => X"8F07",
      LOC => "SLICE_X29Y24"
    )
    port map (
      ADR0 => offset_s_cmp_ge0000,
      ADR1 => offset_s_cmp_ge0001,
      ADR2 => N71,
      ADR3 => R_i_6_IBUF_1305,
      O => max_s(6)
    );
  diff_nominat_s_mux0001_2_SW0 : X_LUT4
    generic map(
      INIT => X"DF80",
      LOC => "SLICE_X24Y20"
    )
    port map (
      ADR0 => offset_s_cmp_ge0003,
      ADR1 => R_i_2_IBUF_1280,
      ADR2 => offset_s_cmp_ge0002,
      ADR3 => G_i_2_IBUF_1284,
      O => N33
    );
  diff_nominat_s_mux0000_5_Q : X_LUT4
    generic map(
      INIT => X"F870",
      LOC => "SLICE_X25Y25"
    )
    port map (
      ADR0 => offset_s_cmp_ge0000,
      ADR1 => offset_s_cmp_ge0001,
      ADR2 => N89,
      ADR3 => G_i_5_IBUF_1312,
      O => diff_nominat_s_mux0000(5)
    );
  max_s_3_Q : X_LUT4
    generic map(
      INIT => X"80F7",
      LOC => "SLICE_X26Y24"
    )
    port map (
      ADR0 => offset_s_cmp_ge0001,
      ADR1 => offset_s_cmp_ge0000,
      ADR2 => R_i_3_IBUF_1317,
      ADR3 => N77,
      O => max_s(3)
    );
  diff_nominat_s_mux0000_2_Q : X_LUT4
    generic map(
      INIT => X"BF80",
      LOC => "SLICE_X25Y21"
    )
    port map (
      ADR0 => G_i_2_IBUF_1284,
      ADR1 => offset_s_cmp_ge0001,
      ADR2 => offset_s_cmp_ge0000,
      ADR3 => N95,
      O => diff_nominat_s_mux0000(2)
    );
  min_s_5_Q : X_LUT4
    generic map(
      INIT => X"D155",
      LOC => "SLICE_X28Y24"
    )
    port map (
      ADR0 => N59,
      ADR1 => min_s_cmp_le0001,
      ADR2 => R_i_5_IBUF_1313,
      ADR3 => min_s_cmp_le0000,
      O => min_s(5)
    );
  max_s_0_Q : X_LUT4
    generic map(
      INIT => X"80F7",
      LOC => "SLICE_X26Y22"
    )
    port map (
      ADR0 => offset_s_cmp_ge0000,
      ADR1 => offset_s_cmp_ge0001,
      ADR2 => R_i_0_IBUF_1301,
      ADR3 => N83,
      O => max_s(0)
    );
  min_s_7_Q : X_LUT4
    generic map(
      INIT => X"C555",
      LOC => "SLICE_X31Y25"
    )
    port map (
      ADR0 => N55,
      ADR1 => R_i_7_IBUF_1271,
      ADR2 => min_s_cmp_le0001,
      ADR3 => min_s_cmp_le0000,
      O => min_s(7)
    );
  max_s_2_Q : X_LUT4
    generic map(
      INIT => X"D155",
      LOC => "SLICE_X26Y25"
    )
    port map (
      ADR0 => N79,
      ADR1 => offset_s_cmp_ge0001,
      ADR2 => R_i_2_IBUF_1280,
      ADR3 => offset_s_cmp_ge0000,
      O => max_s(2)
    );
  diff_nominat_s_mux0000_1_Q : X_LUT4
    generic map(
      INIT => X"EA2A",
      LOC => "SLICE_X25Y23"
    )
    port map (
      ADR0 => N97,
      ADR1 => offset_s_cmp_ge0001,
      ADR2 => offset_s_cmp_ge0000,
      ADR3 => G_i_1_IBUF_1287,
      O => diff_nominat_s_mux0000(1)
    );
  min_s_4_Q : X_LUT4
    generic map(
      INIT => X"80F7",
      LOC => "SLICE_X30Y24"
    )
    port map (
      ADR0 => min_s_cmp_le0000,
      ADR1 => min_s_cmp_le0001,
      ADR2 => R_i_4_IBUF_1292,
      ADR3 => N61,
      O => min_s(4)
    );
  min_s_1_Q : X_LUT4
    generic map(
      INIT => X"80F7",
      LOC => "SLICE_X31Y23"
    )
    port map (
      ADR0 => min_s_cmp_le0001,
      ADR1 => min_s_cmp_le0000,
      ADR2 => R_i_1_IBUF_1288,
      ADR3 => N67,
      O => min_s(1)
    );
  min_s_2_Q : X_LUT4
    generic map(
      INIT => X"8D0F",
      LOC => "SLICE_X31Y22"
    )
    port map (
      ADR0 => min_s_cmp_le0001,
      ADR1 => R_i_2_IBUF_1280,
      ADR2 => N65,
      ADR3 => min_s_cmp_le0000,
      O => min_s(2)
    );
  diff_nominat_s_mux0001_3_SW0 : X_LUT4
    generic map(
      INIT => X"F780",
      LOC => "SLICE_X25Y22"
    )
    port map (
      ADR0 => offset_s_cmp_ge0002,
      ADR1 => offset_s_cmp_ge0003,
      ADR2 => R_i_3_IBUF_1317,
      ADR3 => G_i_3_IBUF_1319,
      O => N31
    );
  diff_nominat_s_mux0000_6_Q : X_LUT4
    generic map(
      INIT => X"CAAA",
      LOC => "SLICE_X28Y23"
    )
    port map (
      ADR0 => N87,
      ADR1 => G_i_6_IBUF_1307,
      ADR2 => offset_s_cmp_ge0001,
      ADR3 => offset_s_cmp_ge0000,
      O => diff_nominat_s_mux0000(6)
    );
  max_s_4_Q : X_LUT4
    generic map(
      INIT => X"80DF",
      LOC => "SLICE_X25Y24"
    )
    port map (
      ADR0 => offset_s_cmp_ge0000,
      ADR1 => R_i_4_IBUF_1292,
      ADR2 => offset_s_cmp_ge0001,
      ADR3 => N75,
      O => max_s(4)
    );
  diff_nominat_s_mux0000_3_Q : X_LUT4
    generic map(
      INIT => X"EA2A",
      LOC => "SLICE_X25Y20"
    )
    port map (
      ADR0 => N93,
      ADR1 => offset_s_cmp_ge0001,
      ADR2 => offset_s_cmp_ge0000,
      ADR3 => G_i_3_IBUF_1319,
      O => diff_nominat_s_mux0000(3)
    );
  min_s_6_Q : X_LUT4
    generic map(
      INIT => X"8D0F",
      LOC => "SLICE_X31Y24"
    )
    port map (
      ADR0 => min_s_cmp_le0001,
      ADR1 => R_i_6_IBUF_1305,
      ADR2 => N57,
      ADR3 => min_s_cmp_le0000,
      O => min_s(6)
    );
  max_s_1_Q : X_LUT4
    generic map(
      INIT => X"80F7",
      LOC => "SLICE_X29Y23"
    )
    port map (
      ADR0 => offset_s_cmp_ge0000,
      ADR1 => offset_s_cmp_ge0001,
      ADR2 => R_i_1_IBUF_1288,
      ADR3 => N81,
      O => max_s(1)
    );
  diff_nominat_s_mux0000_0_Q : X_LUT4
    generic map(
      INIT => X"EA2A",
      LOC => "SLICE_X26Y23"
    )
    port map (
      ADR0 => N99,
      ADR1 => offset_s_cmp_ge0000,
      ADR2 => offset_s_cmp_ge0001,
      ADR3 => G_i_0_IBUF_1300,
      O => diff_nominat_s_mux0000(0)
    );
  min_s_3_Q : X_LUT4
    generic map(
      INIT => X"B133",
      LOC => "SLICE_X30Y22"
    )
    port map (
      ADR0 => min_s_cmp_le0000,
      ADR1 => N63,
      ADR2 => R_i_3_IBUF_1317,
      ADR3 => min_s_cmp_le0001,
      O => min_s(3)
    );
  min_s_0_Q : X_LUT4
    generic map(
      INIT => X"8D0F",
      LOC => "SLICE_X30Y23"
    )
    port map (
      ADR0 => min_s_cmp_le0000,
      ADR1 => R_i_0_IBUF_1301,
      ADR2 => N69,
      ADR3 => min_s_cmp_le0001,
      O => min_s(0)
    );
  Madd_Y_large_s_Madd_lut_0_Q : X_LUT4
    generic map(
      INIT => X"55AA",
      LOC => "SLICE_X35Y20"
    )
    port map (
      ADR0 => Madd_Y_large_s_addsub0000_Madd_lut_0_0,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => B_output_s(0),
      O => Madd_Y_large_s_Madd_lut(0)
    );
  Madd_Y_large_s_Madd_lut_2_Q : X_LUT4
    generic map(
      INIT => X"6666",
      LOC => "SLICE_X35Y21"
    )
    port map (
      ADR0 => B_output_s(2),
      ADR1 => Y_large_s_addsub0000(2),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Madd_Y_large_s_Madd_lut(2)
    );
  Madd_Y_large_s_Madd_lut_4_Q : X_LUT4
    generic map(
      INIT => X"33CC",
      LOC => "SLICE_X35Y22"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Y_large_s_addsub0000(4),
      ADR2 => VCC,
      ADR3 => B_output_s(4),
      O => Madd_Y_large_s_Madd_lut(4)
    );
  Madd_Y_large_s_Madd_lut_6_Q : X_LUT4
    generic map(
      INIT => X"55AA",
      LOC => "SLICE_X35Y23"
    )
    port map (
      ADR0 => Y_large_s_addsub0000(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => B_output_s(6),
      O => Madd_Y_large_s_Madd_lut(6)
    );
  Madd_Y_large_s_Madd_lut_8_Q : X_LUT4
    generic map(
      INIT => X"6666",
      LOC => "SLICE_X35Y24"
    )
    port map (
      ADR0 => Y_large_s_addsub0000(8),
      ADR1 => B_output_s(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Madd_Y_large_s_Madd_lut(8)
    );
  Madd_Y_large_s_Madd_lut_10_Q : X_LUT4
    generic map(
      INIT => X"3C3C",
      LOC => "SLICE_X35Y25"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Y_large_s_addsub0000(10),
      ADR2 => B_output_s(10),
      ADR3 => VCC,
      O => Madd_Y_large_s_Madd_lut(10)
    );
  Madd_Y_large_s_Madd_lut_12_Q : X_LUT4
    generic map(
      INIT => X"6666",
      LOC => "SLICE_X35Y26"
    )
    port map (
      ADR0 => B_output_s(12),
      ADR1 => Y_large_s_addsub0000(12),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Madd_Y_large_s_Madd_lut(12)
    );
  Mcompar_min_s_cmp_le0001_lut_6_Q : X_LUT4
    generic map(
      INIT => X"AA55",
      LOC => "SLICE_X39Y27"
    )
    port map (
      ADR0 => B_i_6_IBUF_1306,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => R_i_6_IBUF_1305,
      O => Mcompar_min_s_cmp_le0001_lut(6)
    );
  Msub_diff_min_max_s_lut_0_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X27Y22"
    )
    port map (
      ADR0 => min_s_0_0,
      ADR1 => max_s_0_0,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Msub_diff_min_max_s_lut(0)
    );
  Msub_diff_min_max_s_lut_2_Q : X_LUT4
    generic map(
      INIT => X"AA55",
      LOC => "SLICE_X27Y23"
    )
    port map (
      ADR0 => max_s_2_0,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => min_s_2_0,
      O => Msub_diff_min_max_s_lut(2)
    );
  Msub_diff_min_max_s_lut_4_Q : X_LUT4
    generic map(
      INIT => X"AA55",
      LOC => "SLICE_X27Y24"
    )
    port map (
      ADR0 => max_s_4_0,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => min_s_4_0,
      O => Msub_diff_min_max_s_lut(4)
    );
  Madd_Y_large_s_Madd_lut_14_Q : X_LUT4
    generic map(
      INIT => X"3C3C",
      LOC => "SLICE_X35Y27"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Y_large_s_addsub0000(14),
      ADR2 => B_output_s(14),
      ADR3 => VCC,
      O => Madd_Y_large_s_Madd_lut(14)
    );
  Mcompar_min_s_cmp_le0001_lut_0_Q : X_LUT4
    generic map(
      INIT => X"A5A5",
      LOC => "SLICE_X39Y24"
    )
    port map (
      ADR0 => B_i_0_IBUF_1326,
      ADR1 => VCC,
      ADR2 => R_i_0_IBUF_1301,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0001_lut(0)
    );
  Mcompar_min_s_cmp_le0001_lut_2_Q : X_LUT4
    generic map(
      INIT => X"C3C3",
      LOC => "SLICE_X39Y25"
    )
    port map (
      ADR0 => VCC,
      ADR1 => B_i_2_IBUF_1282,
      ADR2 => R_i_2_IBUF_1280,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0001_lut(2)
    );
  Mcompar_min_s_cmp_le0001_lut_4_Q : X_LUT4
    generic map(
      INIT => X"CC33",
      LOC => "SLICE_X39Y26"
    )
    port map (
      ADR0 => VCC,
      ADR1 => B_i_4_IBUF_1293,
      ADR2 => VCC,
      ADR3 => R_i_4_IBUF_1292,
      O => Mcompar_min_s_cmp_le0001_lut(4)
    );
  Msub_diff_nominat_s_lut_0_Q : X_LUT4
    generic map(
      INIT => X"A965",
      LOC => "SLICE_X22Y20"
    )
    port map (
      ADR0 => diff_nominat_s_mux0000_0_0,
      ADR1 => offset_s_0_0,
      ADR2 => B_i_0_IBUF_1326,
      ADR3 => N37_0,
      O => Msub_diff_nominat_s_lut(0)
    );
  Msub_diff_nominat_s_lut_2_Q : X_LUT4
    generic map(
      INIT => X"A965",
      LOC => "SLICE_X22Y21"
    )
    port map (
      ADR0 => diff_nominat_s_mux0000_2_0,
      ADR1 => offset_s_0_0,
      ADR2 => B_i_2_IBUF_1282,
      ADR3 => N33_0,
      O => Msub_diff_nominat_s_lut(2)
    );
  Msub_diff_nominat_s_lut_4_Q : X_LUT4
    generic map(
      INIT => X"A695",
      LOC => "SLICE_X22Y22"
    )
    port map (
      ADR0 => diff_nominat_s_mux0000_4_0,
      ADR1 => offset_s_0_0,
      ADR2 => N29_0,
      ADR3 => B_i_4_IBUF_1293,
      O => Msub_diff_nominat_s_lut(4)
    );
  Msub_diff_nominat_s_lut_6_Q : X_LUT4
    generic map(
      INIT => X"A965",
      LOC => "SLICE_X22Y23"
    )
    port map (
      ADR0 => diff_nominat_s_mux0000_6_0,
      ADR1 => offset_s_0_0,
      ADR2 => B_i_6_IBUF_1306,
      ADR3 => N25_0,
      O => Msub_diff_nominat_s_lut(6)
    );
  Mcompar_offset_s_cmp_ge0001_lut_6_Q : X_LUT4
    generic map(
      INIT => X"C3C3",
      LOC => "SLICE_X33Y25"
    )
    port map (
      ADR0 => VCC,
      ADR1 => R_i_6_IBUF_1305,
      ADR2 => B_i_6_IBUF_1306,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0001_lut(6)
    );
  Mcompar_min_s_cmp_le0003_lut_0_Q : X_LUT4
    generic map(
      INIT => X"C3C3",
      LOC => "SLICE_X36Y22"
    )
    port map (
      ADR0 => VCC,
      ADR1 => B_i_0_IBUF_1326,
      ADR2 => G_i_0_IBUF_1300,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0003_lut(0)
    );
  Mcompar_min_s_cmp_le0003_lut_2_Q : X_LUT4
    generic map(
      INIT => X"A5A5",
      LOC => "SLICE_X36Y23"
    )
    port map (
      ADR0 => B_i_2_IBUF_1282,
      ADR1 => VCC,
      ADR2 => G_i_2_IBUF_1284,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0003_lut(2)
    );
  Mcompar_min_s_cmp_le0003_lut_4_Q : X_LUT4
    generic map(
      INIT => X"A5A5",
      LOC => "SLICE_X36Y24"
    )
    port map (
      ADR0 => B_i_4_IBUF_1293,
      ADR1 => VCC,
      ADR2 => G_i_4_IBUF_1294,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0003_lut(4)
    );
  Mcompar_min_s_cmp_le0003_lut_6_Q : X_LUT4
    generic map(
      INIT => X"CC33",
      LOC => "SLICE_X36Y25"
    )
    port map (
      ADR0 => VCC,
      ADR1 => B_i_6_IBUF_1306,
      ADR2 => VCC,
      ADR3 => G_i_6_IBUF_1307,
      O => Mcompar_min_s_cmp_le0003_lut(6)
    );
  Msub_diff_min_max_s_lut_6_Q : X_LUT4
    generic map(
      INIT => X"CC33",
      LOC => "SLICE_X27Y25"
    )
    port map (
      ADR0 => VCC,
      ADR1 => max_s_6_0,
      ADR2 => VCC,
      ADR3 => min_s_6_0,
      O => Msub_diff_min_max_s_lut(6)
    );
  Mcompar_offset_s_cmp_ge0001_lut_0_Q : X_LUT4
    generic map(
      INIT => X"A5A5",
      LOC => "SLICE_X33Y22"
    )
    port map (
      ADR0 => R_i_0_IBUF_1301,
      ADR1 => VCC,
      ADR2 => B_i_0_IBUF_1326,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0001_lut(0)
    );
  Mcompar_offset_s_cmp_ge0001_lut_2_Q : X_LUT4
    generic map(
      INIT => X"C3C3",
      LOC => "SLICE_X33Y23"
    )
    port map (
      ADR0 => VCC,
      ADR1 => R_i_2_IBUF_1280,
      ADR2 => B_i_2_IBUF_1282,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0001_lut(2)
    );
  Mcompar_offset_s_cmp_ge0001_lut_4_Q : X_LUT4
    generic map(
      INIT => X"CC33",
      LOC => "SLICE_X33Y24"
    )
    port map (
      ADR0 => VCC,
      ADR1 => R_i_4_IBUF_1292,
      ADR2 => VCC,
      ADR3 => B_i_4_IBUF_1293,
      O => Mcompar_offset_s_cmp_ge0001_lut(4)
    );
  Madd_Y_large_s_addsub0000_Madd_lut_12_Q : X_LUT4
    generic map(
      INIT => X"33CC",
      LOC => "SLICE_X34Y24"
    )
    port map (
      ADR0 => VCC,
      ADR1 => R_output_s(12),
      ADR2 => VCC,
      ADR3 => G_output_s(12),
      O => Madd_Y_large_s_addsub0000_Madd_lut(12)
    );
  Madd_Y_large_s_addsub0000_Madd_lut_14_Q : X_LUT4
    generic map(
      INIT => X"6666",
      LOC => "SLICE_X34Y25"
    )
    port map (
      ADR0 => G_output_s(14),
      ADR1 => R_output_s(14),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Madd_Y_large_s_addsub0000_Madd_lut(14)
    );
  Mcompar_offset_s_cmp_ge0003_lut_0_Q : X_LUT4
    generic map(
      INIT => X"A5A5",
      LOC => "SLICE_X29Y26"
    )
    port map (
      ADR0 => G_i_0_IBUF_1300,
      ADR1 => VCC,
      ADR2 => R_i_0_IBUF_1301,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0003_lut(0)
    );
  Mcompar_min_s_cmp_le0000_lut_6_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X38Y27"
    )
    port map (
      ADR0 => R_i_6_IBUF_1305,
      ADR1 => G_i_6_IBUF_1307,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0000_lut(6)
    );
  Madd_Y_large_s_addsub0000_Madd_lut_0_Q : X_LUT4
    generic map(
      INIT => X"6666",
      LOC => "SLICE_X34Y18"
    )
    port map (
      ADR0 => R_output_s(0),
      ADR1 => G_output_s(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Madd_Y_large_s_addsub0000_Madd_lut(0)
    );
  Madd_Y_large_s_addsub0000_Madd_lut_2_Q : X_LUT4
    generic map(
      INIT => X"33CC",
      LOC => "SLICE_X34Y19"
    )
    port map (
      ADR0 => VCC,
      ADR1 => R_output_s(2),
      ADR2 => VCC,
      ADR3 => G_output_s(2),
      O => Madd_Y_large_s_addsub0000_Madd_lut(2)
    );
  Madd_Y_large_s_addsub0000_Madd_lut_4_Q : X_LUT4
    generic map(
      INIT => X"6666",
      LOC => "SLICE_X34Y20"
    )
    port map (
      ADR0 => G_output_s(4),
      ADR1 => R_output_s(4),
      ADR2 => VCC,
      ADR3 => VCC,
      O => Madd_Y_large_s_addsub0000_Madd_lut(4)
    );
  Madd_H_bias_s_Madd_lut_0_Q : X_LUT4
    generic map(
      INIT => X"9595",
      LOC => "SLICE_X6Y22"
    )
    port map (
      ADR0 => H_large_s(9),
      ADR1 => offset_s_cmp_ge0001,
      ADR2 => offset_s_cmp_ge0000,
      ADR3 => VCC,
      O => H_bias_s(0)
    );
  Madd_H_bias_s_Madd_lut_2_Q : X_LUT4
    generic map(
      INIT => X"6CCC",
      LOC => "SLICE_X6Y23"
    )
    port map (
      ADR0 => offset_s_cmp_ge0003,
      ADR1 => H_large_s(11),
      ADR2 => offset_s_0_0,
      ADR3 => offset_s_cmp_ge0002,
      O => Madd_H_bias_s_Madd_lut(2)
    );
  Madd_H_bias_s_Madd_lut_4_Q : X_LUT4
    generic map(
      INIT => X"6CCC",
      LOC => "SLICE_X6Y24"
    )
    port map (
      ADR0 => offset_s_cmp_ge0003,
      ADR1 => H_large_s(13),
      ADR2 => offset_s_0_0,
      ADR3 => offset_s_cmp_ge0002,
      O => Madd_H_bias_s_Madd_lut(4)
    );
  Mcompar_offset_s_cmp_ge0003_lut_2_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X29Y27"
    )
    port map (
      ADR0 => G_i_2_IBUF_1284,
      ADR1 => R_i_2_IBUF_1280,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0003_lut(2)
    );
  Mcompar_offset_s_cmp_ge0003_lut_4_Q : X_LUT4
    generic map(
      INIT => X"CC33",
      LOC => "SLICE_X29Y28"
    )
    port map (
      ADR0 => VCC,
      ADR1 => G_i_4_IBUF_1294,
      ADR2 => VCC,
      ADR3 => R_i_4_IBUF_1292,
      O => Mcompar_offset_s_cmp_ge0003_lut(4)
    );
  Mcompar_offset_s_cmp_ge0003_lut_6_Q : X_LUT4
    generic map(
      INIT => X"CC33",
      LOC => "SLICE_X29Y29"
    )
    port map (
      ADR0 => VCC,
      ADR1 => G_i_6_IBUF_1307,
      ADR2 => VCC,
      ADR3 => R_i_6_IBUF_1305,
      O => Mcompar_offset_s_cmp_ge0003_lut(6)
    );
  Mcompar_offset_s_cmp_ge0000_lut_0_Q : X_LUT4
    generic map(
      INIT => X"C3C3",
      LOC => "SLICE_X36Y26"
    )
    port map (
      ADR0 => VCC,
      ADR1 => R_i_0_IBUF_1301,
      ADR2 => G_i_0_IBUF_1300,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0000_lut(0)
    );
  Mcompar_offset_s_cmp_ge0000_lut_2_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X36Y27"
    )
    port map (
      ADR0 => G_i_2_IBUF_1284,
      ADR1 => R_i_2_IBUF_1280,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0000_lut(2)
    );
  Mcompar_offset_s_cmp_ge0000_lut_4_Q : X_LUT4
    generic map(
      INIT => X"A5A5",
      LOC => "SLICE_X36Y28"
    )
    port map (
      ADR0 => R_i_4_IBUF_1292,
      ADR1 => VCC,
      ADR2 => G_i_4_IBUF_1294,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0000_lut(4)
    );
  Mcompar_offset_s_cmp_ge0000_lut_6_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X36Y29"
    )
    port map (
      ADR0 => R_i_6_IBUF_1305,
      ADR1 => G_i_6_IBUF_1307,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0000_lut(6)
    );
  Mcompar_min_s_cmp_le0002_lut_0_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X37Y24"
    )
    port map (
      ADR0 => R_i_0_IBUF_1301,
      ADR1 => G_i_0_IBUF_1300,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0002_lut(0)
    );
  Mcompar_min_s_cmp_le0002_lut_2_Q : X_LUT4
    generic map(
      INIT => X"CC33",
      LOC => "SLICE_X37Y25"
    )
    port map (
      ADR0 => VCC,
      ADR1 => R_i_2_IBUF_1280,
      ADR2 => VCC,
      ADR3 => G_i_2_IBUF_1284,
      O => Mcompar_min_s_cmp_le0002_lut(2)
    );
  Madd_Y_large_s_addsub0000_Madd_lut_6_Q : X_LUT4
    generic map(
      INIT => X"3C3C",
      LOC => "SLICE_X34Y21"
    )
    port map (
      ADR0 => VCC,
      ADR1 => R_output_s(6),
      ADR2 => G_output_s(6),
      ADR3 => VCC,
      O => Madd_Y_large_s_addsub0000_Madd_lut(6)
    );
  Madd_Y_large_s_addsub0000_Madd_lut_8_Q : X_LUT4
    generic map(
      INIT => X"55AA",
      LOC => "SLICE_X34Y22"
    )
    port map (
      ADR0 => R_output_s(8),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => G_output_s(8),
      O => Madd_Y_large_s_addsub0000_Madd_lut(8)
    );
  Madd_Y_large_s_addsub0000_Madd_lut_10_Q : X_LUT4
    generic map(
      INIT => X"33CC",
      LOC => "SLICE_X34Y23"
    )
    port map (
      ADR0 => VCC,
      ADR1 => R_output_s(10),
      ADR2 => VCC,
      ADR3 => G_output_s(10),
      O => Madd_Y_large_s_addsub0000_Madd_lut(10)
    );
  Mcompar_min_s_cmp_le0002_lut_4_Q : X_LUT4
    generic map(
      INIT => X"A5A5",
      LOC => "SLICE_X37Y26"
    )
    port map (
      ADR0 => R_i_4_IBUF_1292,
      ADR1 => VCC,
      ADR2 => G_i_4_IBUF_1294,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0002_lut(4)
    );
  Mcompar_min_s_cmp_le0002_lut_6_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X37Y27"
    )
    port map (
      ADR0 => R_i_6_IBUF_1305,
      ADR1 => G_i_6_IBUF_1307,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_min_s_cmp_le0002_lut(6)
    );
  Mcompar_offset_s_cmp_ge0002_lut_0_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X32Y22"
    )
    port map (
      ADR0 => G_i_0_IBUF_1300,
      ADR1 => B_i_0_IBUF_1326,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0002_lut(0)
    );
  Mcompar_offset_s_cmp_ge0002_lut_2_Q : X_LUT4
    generic map(
      INIT => X"A5A5",
      LOC => "SLICE_X32Y23"
    )
    port map (
      ADR0 => G_i_2_IBUF_1284,
      ADR1 => VCC,
      ADR2 => B_i_2_IBUF_1282,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0002_lut(2)
    );
  Mcompar_offset_s_cmp_ge0002_lut_4_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X32Y24"
    )
    port map (
      ADR0 => B_i_4_IBUF_1293,
      ADR1 => G_i_4_IBUF_1294,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0002_lut(4)
    );
  Mcompar_offset_s_cmp_ge0002_lut_6_Q : X_LUT4
    generic map(
      INIT => X"9999",
      LOC => "SLICE_X32Y25"
    )
    port map (
      ADR0 => G_i_6_IBUF_1307,
      ADR1 => B_i_6_IBUF_1306,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_offset_s_cmp_ge0002_lut(6)
    );
  diff_nominat_s_mux0000_7_Q : X_LUT4
    generic map(
      INIT => X"B8F0",
      LOC => "SLICE_X24Y25"
    )
    port map (
      ADR0 => G_i_7_IBUF_1275,
      ADR1 => offset_s_cmp_ge0001,
      ADR2 => N85,
      ADR3 => offset_s_cmp_ge0000,
      O => diff_nominat_s_mux0000(7)
    );
  max_s_5_Q : X_LUT4
    generic map(
      INIT => X"80DF",
      LOC => "SLICE_X24Y24"
    )
    port map (
      ADR0 => offset_s_cmp_ge0001,
      ADR1 => R_i_5_IBUF_1313,
      ADR2 => offset_s_cmp_ge0000,
      ADR3 => N73,
      O => max_s(5)
    );
  diff_nominat_s_mux0000_4_Q : X_LUT4
    generic map(
      INIT => X"D8F0",
      LOC => "SLICE_X23Y22"
    )
    port map (
      ADR0 => offset_s_cmp_ge0000,
      ADR1 => G_i_4_IBUF_1294,
      ADR2 => N91,
      ADR3 => offset_s_cmp_ge0001,
      O => diff_nominat_s_mux0000(4)
    );
  GLOBAL_LOGIC0_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  GLOBAL_LOGIC1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  diff_nominat_s_8_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_8_XORF_3092,
      O => diff_nominat_s(8)
    );
  diff_nominat_s_8_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X22Y24"
    )
    port map (
      I0 => diff_nominat_s_8_CYINIT_3091,
      I1 => diff_nominat_s_8_F,
      O => diff_nominat_s_8_XORF_3092
    );
  diff_nominat_s_8_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X22Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => diff_nominat_s_6_CYMUXFAST_3064,
      O => diff_nominat_s_8_CYINIT_3091
    );
  diff_nominat_s_8_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FFFF",
      LOC => "SLICE_X22Y24"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => diff_nominat_s_8_F
    );
  Y_o_1_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD22",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_10_XORF_2317,
      O => Y_o_1_O
    );
  Y_o_2_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD76",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_10_XORG_2305,
      O => Y_o_2_O
    );
  Y_o_3_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD67",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_12_XORF_2356,
      O => Y_o_3_O
    );
  Y_o_4_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD74",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_12_XORG_2344,
      O => Y_o_4_O
    );
  Y_o_5_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD68",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_14_XORF_2395,
      O => Y_o_5_O
    );
  Y_o_6_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD73",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_14_XORG_2383,
      O => Y_o_6_O
    );
  Y_o_7_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD66",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_16_XORF_2410,
      O => Y_o_7_O
    );
  H_o_0_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD20",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_bias_s(0),
      O => H_o_0_O
    );
  H_o_1_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD182",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_bias_s_0_XORG_3115,
      O => H_o_1_O
    );
  H_o_2_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD174",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_bias_s_2_XORF_3166,
      O => H_o_2_O
    );
  H_o_3_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD187",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_bias_s_2_XORG_3156,
      O => H_o_3_O
    );
  H_o_4_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD185",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_bias_s_4_XORF_3205,
      O => H_o_4_O
    );
  H_o_5_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD13",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_bias_s_4_XORG_3195,
      O => H_o_5_O
    );
  H_o_6_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD23",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_bias_s_6_XORF_3236,
      O => H_o_6_O
    );
  H_o_7_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD179",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_bias_s_6_XORG_3225,
      O => H_o_7_O
    );
  Y_o_0_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD171",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_large_s_9_XORG_2268,
      O => Y_o_0_O
    );
  NlwBlock_rgb2hy_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_rgb2hy_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;

